Secure non-volatile memory

1. A memory comprising:

a bistable memory cell having a programmed start-up state; and

logic configured to periodically flip a state of the memory cell, the logic including:

a flip-flop configured to store the state of the memory cell in response to an active state of a flip signal; and

a multiplexer configured to write a complement of a state of the flip-flop into the memory cell in response to the active state of the flip signal.

2. The memory of claim 1 wherein the logic comprises a clock configured to generate the flip signal to trigger a flip of the state of the memory cell.

3. The memory of claim 2 wherein the clock has a period smaller than an acquisition time of an emission microscope.

4. The memory of claim 2 wherein the clock has a period of less than a second.

5. The memory of claim 2 wherein the clock has a period of less than 20 ns.

6. The memory of claim 2 further comprising a divider configured to generate a signal indicative of a parity of the flip signal.

7. The memory of claim 1 wherein the logic is configured to commence periodically flipping of the state of the memory cell after a use threshold period of time has elapsed since a start-up of the memory.

8. The memory of claim 1 wherein the memory cell comprises first and second cross-coupled inverting elements having transistors with substantially similar physical dimensions, with at least one transistor of the first inverting element having an operating characteristic different from an operating characteristic of a corresponding transistor of the second inverting element.

9. The memory of claim 8 wherein the operating characteristic is a threshold voltage.

10. The memory of claim 1 wherein the memory cell comprises first and second cross-coupled inverting elements having transistors with substantially similar physical dimensions, with at least two transistors of the first inverting element having an operating characteristic different from an operating characteristic of corresponding transistors of the second inverting element.

11. The memory of claim 1 wherein the memory cell is one of a plurality of bistable memory cells having programmed start-up states and the logic is configured to periodically flip states of each memory cell of the plurality of memory cells.

12. A system, comprising:

one or more processors; and

a memory having:

a plurality of bistable memory cells having programmed start-up states; and

logic configured to periodically flip states of the plurality of bistable memory cells, the logic including:

a flip-flop configured to store a state of a bistable memory cell of the plurality in response to an active state of a flip signal; and

a multiplexer configured to write a complement of a state of the flip-flop into the bistable memory cell in response to the active state of the flip signal.

13. The system of claim 12 wherein the logic comprises a clock configured to generate the flip signal to trigger flipping of the states of the bistable memory cells.

14. The system of claim 13 further comprising a divider configured to generate a signal indicative of a parity of the flip signal.

15. The system of claim 12 wherein the logic is configured to commence periodically flipping of the states of the bistable memory cells after a use threshold period of time has elapsed since a start-up of the memory.

16. The system of claim 12 wherein the bistable memory cells each comprise first and second cross-coupled inverting elements having transistors with substantially similar physical dimensions, with at least one transistor of the first inverting element having an operating characteristic different from an operating characteristic of a corresponding transistor of the second inverting element.

17. The system of claim 12 wherein the memory is implemented in an integrated circuit.

18. A method, comprising:

reading a bistable memory cell of a memory; and

after reading the bistable memory cell, periodically flipping a state of the bistable memory cell, the periodic flipping including:

storing the state of the bistable memory cell in a flip-flop in response to an active state of a flip signal; and

writing a complement of the state stored in the flip-flop into the bistable memory cell in response to the active state of the flip signal.

19. The method of claim 18 wherein the periodically flipping the state of the bistable memory cell comprises generating a clock signal.

20. The method of claim 19 , comprising re-reading the bistable memory cell.

21. The method of claim 20 , comprising compensating for the periodically flipping of the state of the bistable memory cell.

22. The method of claim 21 wherein the compensating comprises determining a parity of the clock signal.

23. The method of claim 18 wherein,

the reading the bistable memory cell of the memory comprises applying a reset signal to the bistable memory cell and reading an output of the bistable memory cell after the output of the bistable memory cell stabilizes at a programmed state; and

the periodically flipping the state of the bistable memory cell comprising applying the flip signal to the bistable memory cell instead of the reset signal.

24. A system, comprising:

means for reading a bistable memory cell;

means for storing a state of the bistable memory cell in response to an active state of a flip signal; and

means for writing a complement of the state stored in the means for storing into the bistable memory cell.

25. The system of claim 24 , further comprising:

means for programming the state of the bistable memory cell at a start-up of the system.

26. The system of claim 24 , further comprising:

means for compensating for periodic flipping of the state of the bistable memory cell.

27. A non-transitory computer-readable medium containing contents to cause a computing device to perform a method, the method comprising:

reading a state of a bistable memory cell; and

after reading the state of the bistable memory cell, flipping the state of the bistable memory cell based on a periodic signal, the periodic flipping including:

storing the state of the bistable memory cell in a flip-flop in response to an active state of the periodic signal; and

writing a complement of the state stored in the flip-flop into the bistable memory cell in response to the active state of the periodic signal.

28. The non-transitory computer-readable medium of claim 27 wherein the method comprises re-reading a state of the bistable memory cell.

29. The non-transitory computer-readable medium of claim 28 wherein the method comprises compensating for the flipping of the state of the bistable memory cell.