Shallow trench isolation for active devices mounted on a CMOS substrate
View Patent ↗The present invention includes operational amplifier for an active pixel sensor that detects optical energy and generates an analog output that is proportional to the optical energy. The active pixel sensor operates in a number of different modes including: signal integration mode, the reset integration mode, column reset mode, and column signal readout mode. Each mode causes the operational amplifier to see a different output load. Accordingly, the operational amplifier includes a variable feedback circuit to provide compensation that provides sufficient amplifier stability for each operating mode of the active pixel sensor. For instance, the operational amplifier includes a bank of feedback capacitors, one or more of which are selected based on the operating mode to provide sufficient phase margin for stability, but also considering gain and bandwidth requirements of the operating mode.
1. A circuit comprising:
a complementary metal oxide semiconductor (CMOS) substrate;
a first active device mounted on the CMOS substrate;
a second active device mounted on the CMOS substrate;
a shallow trench isolation (STI) etched in the CMOS substrate between the first active device and the second active device, wherein the STI is etched to isolate the first active device from other elements mounted on the CMOS substrate; and
a plurality of metal traces in and around the first active device, the second active device, and the STI, wherein the metal traces are configured to minimize bends and stresses in and around the STI.
2. The circuit of claim 1 , wherein the STI is etched to isolate the first active device from the second active device.
3. The circuit of claim 1 , wherein the STI is etched to reduce leakage current between the first active device and the second active device.
4. The circuit of claim 1 , wherein the first active device is an operational amplifier.
5. The circuit of claim 4 , wherein the operational amplifier has a feedback compensation circuit adjustable for a plurality of operating modes, and wherein the feedback compensation circuit is adjusted to provide a minimum stability for each of the operating modes to prevent the operational amplifier from oscillating.
6. The circuit of claim 1 , wherein crossings between metal layers in the CMOS substrate and polysilicon layers in the CMOS substrate are minimized near edges of at least one of the first active device and the second active device.
7. The circuit of claim 1 , wherein the circuit is an active pixel circuit, and wherein the STI is configured to reduce current leakage between pixels in the active pixel circuit.
8. An active pixel circuit comprising:
a complementary metal oxide semiconductor (CMOS) substrate;
a first active device mounted on the CMOS substrate;
an operational amplifier mounted on the CMOS substrate, the operational amplifier having a feedback compensation circuit adjustable for a plurality of operating modes of the active pixel circuit, the feedback compensation circuit adjusted to provide a minimum stability for each of the operating modes to prevent the operational amplifier from oscillating; and
a shallow trench isolation (STI) etched in the CMOS substrate between the first active device and the operational amplifier, wherein the STI is etched to isolate the first active device from elements of the operational amplifier mounted on the CMOS substrate.
9. The active pixel circuit of claim 8 , wherein the feedback compensation circuit in the operational amplifier includes a bank of capacitors, one or more of which capacitors is selected based on the operating modes.
10. The active pixel circuit of claim 8 , wherein the operating modes comprise signal integration mode, reset integration mode, column reset mode, and column signal readout mode.
11. The active pixel circuit of claim 8 , further comprising a pre-charging circuit that pre-charges an output stage of the operational amplifier.
12. The active pixel circuit of claim 8 , wherein the operational amplifier comprises:
a first amplifier stage that receives a differential input signal for amplification;
a second amplifier stage that receives the amplified output from the first amplifier stage and provides a second stage of amplification;
a compensation capacitor bank;
an internal pre-charging portion; and
an output amplifier stage coupled to the output of the second amplifier stage, the compensation capacitor bank, and the pre-charging portion,
wherein the pre-charging portion is operable to improve the pull-up slew rate of the output amplifier stage.
13. The active pixel circuit of claim 8 , wherein the STI is etched to isolate the first active device from the operational amplifier.
14. The active pixel circuit of claim 8 , wherein the STI is etched to reduce leakage current between the first active device and the operational amplifier.
15. The active pixel circuit of claim 8 , further comprising a plurality of metal traces in and around the first active device, the operational amplifier, and the STI, wherein the metal traces are configured to minimize bends and stresses in and around the STI.
16. The active pixel circuit of claim 15 , wherein crossings between the metal traces are minimized near at least one of the first active device and the operational amplifier.
17. The active pixel circuit of claim 15 , wherein the first active device, the operational amplifier, the STI, and the metal traces are integrated on the CMOS substrate, and wherein the CMOS substrate is fabricated using a conventional CMOS process.
18. The active pixel circuit of claim 8 , wherein crossings between metal layers in the CMOS substrate and polysilicon layers in the CMOS substrate are minimized near edges of at least one of the first active device and the operational amplifier.
19. The active pixel circuit of claim 8 , wherein the STI is configured to reduce current leakage between pixels in the active pixel circuit.
20. A circuit comprising:
a complementary metal oxide semiconductor (CMOS) substrate;
a first active device mounted on the CMOS substrate;
a second active device mounted on the CMOS substrate, wherein crossings between metal layers in the CMOS substrate and polysilicon layers in the CMOS substrate are minimized near edges of at least one of the first active device and the second active device; and
a shallow trench isolation (STI) etched in the CMOS substrate between the first active device and the second active device, wherein the STI is etched to isolate the first active device from other elements mounted on the CMOS substrate.