IP Library Granted Patent US 9,882,399
Granted Patent B2
US 9,882,399 · App. 13/297,551 · Granted Jan 30, 2018

Power source generation circuit and integrated circuit

Inventors: Eiichi Sadayuki (Osaka, JP); Kazuki Yoshioka (Osaka, JP)
Assignee: PANASONIC CORPORATION
H02J7/00G05F1/56Y10T307/826Y10T307/832Y10T307/858
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Quick Facts
Patent No.
US 9,882,399
App. No.
13/297,551
Granted
Jan 30, 2018
Kind
B2
Abstract

A power source generation circuit includes a regulator circuit which receives an external power source voltage VDDA from an external power source, and generates a predetermined internal power source voltage on a given terminal VDD; and a charging circuit which connects the external power source and the given terminal when the external power source voltage VDDA supplied from the external power source is equal to or lower than a predetermined threshold voltage.

Claims (68)

1. A power source generation circuit comprising:

a regulator circuit which receives an external power source voltage from an external power source, generates a predetermined internal power source voltage on a given terminal, and includes a first switching transistor, one of a source and a drain of the first switching transistor being connected to the external power source; and

a charging circuit which is connected to the external power source, and connects the external power source and the given terminal when the external power source voltage received from the external power source is equal to or lower than a first threshold voltage,

wherein the charging circuit is configured to supply the external power voltage to the given terminal before the regulator circuit generates the predetermined internal power source voltage on the given terminal.

2. The power source generation circuit according to claim 1 , wherein:

the charging circuit includes a second switching transistor, one of a source and a drain of the second switching transistor being connected to the external power source and another one of the source and the drain of the second switching transistor being connected to the given terminal, and

the second transistor turns ON when the external power source voltage is equal to or lower than the first threshold voltage and turns OFF when the external power source voltage exceeds the first threshold voltage.

3. The power source generation circuit according to claim 2 , wherein the charging circuit includes:

a first resistor having one terminal connected to the external power source;

a second resistor having one terminal connected to a ground;

a diode having an anode connected to another terminal of the first resistor and a cathode connected to the ground;

a first p-type Metal Oxide Semiconductor (MOS) transistor having a gate connected to the anode of the diode, a source connected to the external power source, and a drain connected to another terminal of the second resistor; and

a second p-type MOS transistor being the second switching transistor, and having a gate connected to the drain of the first p-type MOS transistor, a source connected to the external power source, and a drain connected to the given terminal.

4. The power source generation circuit according to claim 1 , wherein the first threshold voltage is lower than the internal power source voltage.

5. The power source generation circuit according to claim 1 , further comprising a trigger signal outputting unit configured to output a predetermined trigger signal to cut connection by the charging circuit between the given terminal and the external power source.

6. The power source generation circuit according to claim 5 , wherein:

the trigger signal outputting unit includes a delay circuit which receives a starting signal for starting up the power source generation circuit, delays the received starting signal by a given time period, and outputs the delayed starting signal as the trigger signal to the charging circuit, and

the charging circuit cuts a connection between the given terminal and the external power source based on the starting signal delayed by the delay circuit.

7. The power source generation circuit according to claim 5 , wherein:

the trigger signal outputting unit includes a voltage detecting circuit which outputs a voltage detecting signal as the trigger signal to the charging circuit when a voltage generated on the given terminal is equal to or higher than a second threshold voltage lower than the internal power source voltage, and

the charging circuit cuts a connection between the given terminal and the external power source based on the voltage detecting signal outputted by the voltage detecting circuit.

8. The power source generation circuit according to claim 6 , wherein:

the charging circuit includes a second switching transistor, one of a source and a drain of the second switching transistor being connected to the external power source and another one of the source and the drain of the second switching transistor being connected to the given terminal, and

the second switching transistor turns ON when the external power source voltage is equal to or lower than the first threshold voltage and turns OFF when the external power source voltage exceeds the first threshold voltage or based on the trigger signal.

9. The power source generation circuit according to claim 8 , wherein the charging circuit includes:

a first resistor having one terminal connected to the external power source;

a second resistor having one terminal connected to a ground;

a diode having an anode connected to another terminal of the first resistor and a cathode connected to the ground;

a first p-type MOS transistor having a gate connected to the anode of the diode, a source connected to the external power source, and a drain connected to another terminal of the second resistor;

a second p-type MOS transistor being the second switching transistor, and having a gate connected to the drain of the first p-type MOS transistor, a source connected to the external power source, and a drain connected to the given terminal; and

an n-type MOS transistor having a gate receiving the trigger signal, a drain connected to the gate of the first p-type MOS transistor, and a source connected to the ground.

10. An integrated circuit comprising:

a regulator circuit which receives a pulsed external power source voltage from an external circuit, generates a predetermined internal power source voltage on a given terminal, and includes a first switching transistor, one of a source and a drain of the first switching transistor being connected to the external circuit; and

a charging circuit which is connected to the external circuit and, connects the external circuit and the given terminal when an external power source voltage received from the external circuit is equal to or lower than a predetermined threshold voltage,

wherein the charging circuit is configured to output the pulsed external power voltage to the given terminal before the regulator circuit generates the predetermined internal power source voltage on the given terminal.

11. An integrated circuit comprising:

a regulator circuit which receives an external power source voltage from an external power source and provides a predetermined power source voltage generated internally, and includes a first switching transistor, a source of the first switching transistor being connected to the external power source; and

a charging circuit which includes a second switching transistor having a source connected to the external power source and a drain connected to a first terminal, wherein:

the second switching transistor turns ON to provide the external power source voltage received from the external power source to the first terminal via the second switching transistor when the external power source voltage is below a predetermined threshold voltage,

the first switching transistor is a first p-type Metal Oxide Semiconductor (MOS) transistor,

the second switching transistor is a second p-type MOS transistor having a gate that is controlled based on the external power source voltage and a variable input signal,

a source-drain path of the first p-type MOS transistor and a source-drain path of the second p-type MOS transistor are not connected in series, and

the charging circuit is configured to supply the external power source voltage to the first terminal before the regulator circuit generates the predetermined power source voltage on the first terminal.

12. The integrated circuit according to claim 11 , wherein a drain of the first p-type MOS transistor and a drain of the second p-type MOS transistor are connected in common to a capacitor.

13. The integrated circuit according to claim 12 , wherein the drain of the first p-type MOS transistor and the drain of the second p-type MOS transistor are connected in common to a capacitor via a third terminal.

14. The integrated circuit according to claim 11 , wherein the second switching transistor can be controlled by a single external input signal.

15. The integrated circuit according to claim 14 , wherein the second switching transistor can be turned OFF by the single external input signal.

16. The integrated circuit according to claim 11 , wherein the second switching transistor can be automatically turned OFF based on a voltage detected internally.

17. The integrated circuit according to claim 11 , wherein:

the variable input signal is applied to a second terminal, and

the second terminal is not on a path between the gate of the second p-type MOS transistor and the external power source.

18. The integrated circuit according to claim 11 , wherein a gate signal applied to the gate of the second p-type MOS transistor controlled based on the external power source voltage and the variable input signal is not supplied to the regulator circuit.

19. An integrated circuit comprising:

a regulator circuit which receives an external power source voltage from an external power source and provides a predetermined power source voltage generated internally, and includes a first switching transistor, one of a source and a drain of the first switching transistor being connected to the external power source; and

a charging circuit which includes a second switching transistor with one of a source and a drain connected to the external power source and another of the source and the drain connected to a first terminal, wherein:

the second switching transistor turns ON to provide the external power source voltage received from the external power source to the first terminal via the second switching transistor when the external power source voltage is below a predetermined threshold voltage,

the first switching transistor is a first Metal Oxide Semiconductor (MOS) transistor,

the second switching transistor is a second MOS transistor having a gate controlled based on the external power source voltage and a variable input signal applied to a second terminal,

the second terminal is not on a path between the gate of the second MOS transistor and the external power source, and

the charging circuit is configured to supply the external power source voltage to the first terminal before the regulator circuit generates the predetermined power source voltage on the first terminal.

20. The integrated circuit according to claim 19 , wherein a gate signal applied to the gate of the second MOS transistor controlled based on the external power source voltage and the variable input signal is not supplied to the regulator circuit.

21. An integrated circuit comprising:

a first circuit which receives an external power source voltage from an external power source and provides a predetermined power source voltage generated internally, and includes a first Metal Oxide Semiconductor (MOS) transistor, one of a source and a drain of the first MOS transistor being connected to the external power source; and

a second circuit which includes a second MOS transistor with one of a source and a drain connected to the external power source and another of the source and the drain connected to a first terminal, wherein:

the second MOS transistor turns ON to provide the external power source voltage received from the external power source to the first terminal via the second MOS transistor when the external power source voltage is below a predetermined threshold voltage,

a gate signal applied to a gate of the second MOS transistor is controlled based on the external power source voltage and a variable signal,

the gate signal is not supplied to the first circuit, and

the charging circuit is configured to supply the external power source voltage to the first terminal before the regulator circuit generates the predetermined power source voltage on the first terminal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2026
From: PANASONIC HOLDINGS CORPORATION
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 074237/0726 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2012
From: SADAYUKI, EIICHI; YOSHIOKA, KAZUKI
To: PANASONIC CORPORATION
Reel/Frame 027588/0045 →
Priority Claims (1)
JP 2009-121310 · May 19, 2009 · national
Continuity (2)
Continuation PCTJP2010000225 · Jan 18, 2010
Related Publication 20120062185A1 · Mar 15, 2012