CARD READER WITH EFFICIENT ENCRYPTION
A card reader has a housing, read head and device electronics that receive a raw signal from the read head and converts it into a processed digital signal that the microcontroller can interpret. A microcontroller with associated logic resources and code receives a digital signal from the device electronics and creates an encrypted and signed message based on the contents of the signal. An output jack is provided.
1 . A card reader, comprising:
a housing;
a read head;
device electronics that receive a raw signal from the read head and convert it into a processed digital signal that the microcontroller can interpret;
a microcontroller with associated logic resources and code that receives a digital signal from the device electronics and creates an encrypted and signed message based on the contents of the signal; and
an output jack.
2 . The card reader of claim 1 , wherein the messages created can contain both encrypted and non-encrypted data, and contain a signature that can be used to verify that the data has not been modified.
3 . The card reader of claim 1 , wherein the microcontroller code uses a block cipher for encryption and signing.
4 . The card reader of claim 1 wherein the microcontroller uses the CCFB+H cipher mode for encryption and signing.
5 . The card reader of claim 1 , wherein the microcontroller code includes a unique identifier and cryptographic key.
6 . The card reader of claim 1 , wherein the code inspects itself to see if it, its cryptographic key, or its identifier has been modified.
7 . The card reader of claim 1 , wherein the code includes countermeasures to detect tampering and attacks on the card reader.
8 . The card reader of claim 1 , wherein the card reader disables itself when modification or tampering is detected.
9 . The card reader of claim 1 , wherein the code is no more than 8 kilobytes in size.
10 . The card reader of claim 1 , wherein the cryptographic key is expanded before programming, and the microcontroller code does not include or require key expansion functionality.
11 . The card reader of claim 1 , wherein the microcontroller is configured to recalculate the bit period in real time to capture variable-speed swipes.
12 . The card reader of claim 1 , wherein the microcontroller is configured to parse and error-check card data.
13 . The card reader of claim 1 , wherein the microcontroller is configured to run periodic checksums on code and memory.
14 . The card reader of claim 1 , wherein the microcontroller uses thresholds to filter out erroneous data and/or false edges.
15 . The card reader of claim 1 , wherein the microcontroller is configured to determine 1's and 0's by checking the frequency of polarity changes within a bit period.
16 . The card reader of claim 1 , wherein the device electronics includes the microcontroller and an analog to digital front-end.
17 . The card reader of claim 2 , wherein the analog to digital front end is coupled to a processing element in the microcontroller, the analog to digital front end receiving a raw magnetic head signal and converting the raw magnetic head signal into a processed digital signal that the microcontroller can interpret, the microcontroller producing a signal.
18 . The card reader of claim 1 , wherein the front end includes, an amplifier/filter, differentiator and a comparator.
19 . The card reader of claim 18 , wherein the front end further includes wake-up electronics.
20 . The card reader of claim 19 , wherein the wake-up electronics is a wake-up circuit.
21 . The card reader of claim 1 , wherein the output jack signal is a synchronous Manchester encoded stream.
22 . The card reader of claim 1 , wherein the output jack signal is an asynchronized stream.
23 . The card reader of claim 1 , wherein the output jack signal is at a frequency that the output jack signal appears to look AC to a microphone input of the mobile device.
24 . The card reader of claim 1 , wherein a frequency of the output jack signal is 2 KHz to 48 kHz.
25 . The card reader of claim 1 , wherein a frequency of the output jack signal is 2.4 kHz.
26 . The card reader of claim 1 , wherein the microcontroller has a non-volatile memory with a size of 2-8 kbytes, and RAM with a size 128-512 bytes.
27 . The card reader of claim 1 , wherein the analog to digital front end is configured to capture card readings that are swept at a rate of 5 inches to 50 inches per second.
28 . The card reader of claim 1 , wherein the read head sends the output jack signal to the mobile device at a constant baud rate.
29 . The card reader of claim 28 , wherein the constant baud rate is 2400 to 9200 baud.
30 . The card reader of claim 19 , further comprising:
a power source coupled to the wake-up electronics.