PCIe NVRAM card based on NVDIMM

1. A memory system controller, comprising:

one or more sockets for accommodating non-volatile dual in-line memory module (NVDIMM) cards;

a peripheral component interconnect express (PCIe) interface for coupling the memory system controller to a host system;

a controller coupled to the PCIe interface over a PCIe-compliant connection and to the one or more sockets over respective double data rate (DDR2) connections, said controller configured to:

manage data transfers between the host system and a specified one of the NVDIMM sockets in which an NVDIMM card is accommodated as direct memory access (DMA) reads and writes,

format data received from the PCIe interface for transmission to the specified NVDIMM socket over the corresponding one or more DDR2 connections, and

initiate save and restore operations on the NVDIMM card accommodated within the specified NVDIMM socket in response to power failure and power restoration indications; and

power detection logic coupled to the PCIe interface and the controller and configured to detect and provide the controller with said power failure and power restoration indications,

wherein the controller is configured as PCIe-to-DDR interface logic between a PCIe end point and a DDR2 controller for managing register read and write operations, generating memory read requests to host system for DMA operations, receiving completion packets for read requests generated, transmitting TLPs to a PCIe block, PCIe address management, scatter gather list (SGL) management, DMA descriptor management, managing read and write data buffers, and managing a DDR2 controller interface.

2. The memory system controller of claim 1 , wherein the controller comprises a field programmable gate array (FPGA).

3. The memory system controller of claim 2 , wherein the FPGA includes a DMA engine configured to reformat data received over the PCIe bus to comply with DDR2 memory interface requirements for the NVDIMM card.

4. The memory system controller of claim 1 , wherein a first one of the NVDIMM sockets is a 240-pin NVDIMM DDR2 RDIMM socket, and a second one of the NVDIMM sockets is a 244-pin DDR2 Mini RDIMM socket.

5. The memory system controller of claim 1 , further comprising resistor loads coupled to the controller for configuring the memory system controller according to the NVDIMM card.

6. The memory system controller of claim 1 , wherein the controller is configured to issue two-wire interface (TWI) write and read commands to the NVDIMM sockets.

7. The memory system controller of claim 1 , wherein the PCIe-to-DDR interface logic includes a system-to-card (S2C) DMA engine, which manages DMA write operations, and a card-to-system (C2S) DMA engine, which manages DMA read operations.