Gallium nitride devices with electrically conductive regions
View Patent ↗Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., PET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
1. A semiconductor device comprising:
a substrate;
a gallium nitride region formed on said substrate;
a first electrical contact comprising aluminum formed on said gallium nitride region;
an electrically conductive layer comprising aluminum formed over, at least a portion of, said substrate;
a barrier layer separating said electrically conductive layer from said substrate; and
wherein an electrically conductive layer comprises at least a portion of said barrier layer.
2. The semiconductor device of claim 1 , wherein said substrate comprises silicon.
3. The semiconductor device of claim 1 , further comprising a passivating layer formed over said gallium nitride region.
4. The semiconductor device of claim 1 , wherein said semiconductor structure is a transistor and further comprises a source electrode, a drain electrode and a gate electrode, wherein said first electrical contact is electrically connected to said source electrode.
5. The semiconductor device of claim 4 , wherein said gate electrode is defined by an electrode-defining layer comprising silicon nitride.
6. The semiconductor device of claim 1 , further comprising a transition layer formed between said substrate and said gallium nitride region.
7. The semiconductor device of claim 6 , wherein said transition layer is compositionally-graded.
8. The semiconductor device of claim 6 , further comprising a silicon nitride layer formed between said substrate and said transition layer.
9. A semiconductor device comprising:
a silicon substrate;
a gallium nitride region formed on said silicon substrate;
a first electrical contact comprising aluminum formed on said gallium nitride region;
an electrically conductive layer formed over, at least a portion of, said silicon substrate;
a barrier layer separating said electrically conductive layer comprising aluminum from said silicon substrate, wherein a via is formed in said semiconductor device and said electrically conductive layer and said barrier layer are formed on sidewalls of said via; and
wherein an electrically conductive pathway between said first electrical contact and said electrically conductive layer comprises at least a portion of said barrier layer.
10. The semiconductor device of claim 9 , further comprising a passivating layer formed over said gallium nitride region.
11. The semiconductor device of claim 9 , wherein said semiconductor device is a transistor and further comprises a source electrode, a drain electrode and a gate electrode, wherein said first electrical contact is electrically connected to said source electrode.
12. The semiconductor device of claim 11 , wherein said gate electrode is defined by an electrode-defining layer comprising silicon nitride.
13. The semiconductor device of claim 9 , further comprising a transition layer formed between said silicon substrate and said gallium nitride region.
14. The semiconductor device of claim 13 , wherein said transition layer is compositionally-graded.
15. The semiconductor device of claim 13 , further comprising a silicon nitride layer formed between said silicon substrate and said transition layer.