Thin film transistor, pixel structure and method for fabricating the same
A thin film transistor (TFT) that includes a gate, an oxide semiconductor layer, a gate insulator, a source, and a drain is provided. The gate insulator is located between the oxide semiconductor layer and the gate. The source and the drain are in contact with different portions of the oxide semiconductor layer. Each of the source and the drain has a ladder-shaped sidewall that is partially covered by the oxide semiconductor layer. A method for fabricating the above-mentioned TFT is also provided.
1. A method for fabricating a thin film transistor, comprising:
sequentially forming a gate and a gate insulator on a substrate, the gate insulator covering the gate;
forming a source electrode and a drain electrode on the gate insulator, the source electrode and the drain electrode respectively having a ladder-shaped sidewall, wherein an entire lower surface of the source electrode and an entire lower surface of the drain electrode are substantially planar, and each of the source electrode and the drain electrode is a single one layer; and
forming an oxide semiconductor layer on the gate insulator to cover at least one portion of the ladder-shaped sidewall of the source electrode and at least one portion of the ladder-shaped sidewall of the drain electrode, wherein the source electrode and the drain electrode are respectively in contact with different portions of the oxide semiconductor layer.
2. The method for fabricating the thin film transistor as recited in claim 1 , wherein the ladder-shaped sidewall of each of the first source electrode and the drain electrode has three or more steps.
3. A method for fabricating a thin film transistor, comprising:
sequentially forming a gate and a gate insulator on a substrate, the gate insulator covering the gate;
forming a source electrode and a drain electrode on the gate insulator, the source electrode and the drain electrode respectively having a ladder-shaped sidewall, wherein the step comprises:
(a) forming a conductive material layer on the gate insulator;
(b) forming a patterned photoresist layer on the conductive material layer and exposing a portion of the conductive material layer;
(c) partially removing the portion of the conductive material layer exposed by the patterned photoresist layer with use of the patterned photoresist layer as a mask, so as to form a recess pattern in the conductive material layer;
(d) removing a portion of the patterned photoresist layer to form a residual patterned photoresist layer, the residual patterned photoresist layer further exposing a portion of the conductive material layer covered by the patterned photoresist layer; and
(e) partially removing the portion of the conductive material layer exposed by the residual patterned photoresist layer with use of the residual patterned photoresist layer as a mask; and
forming an oxide semiconductor layer on the gate insulator to cover at least one portion of the ladder-shaped sidewall of the source electrode and at least one portion of the ladder-shaped sidewall of the drain electrode, wherein the source electrode and the drain electrode are respectively in contact with different portions of the oxide semiconductor layer.
4. The method for fabricating the thin film transistor as recited in claim 3 , wherein an entire top surface of the conductive material layer of step (a) is substantially planar.