Circuit with high-density capacitors using bootstrapped non-metal layer
View Patent ↗A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining. The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit.
1. A switched-capacitor circuit comprising:
a plurality of capacitors configured on a semiconductor, each capacitor of the plurality of capacitors having a respective top plate and a respective bottom plate, with a respective capacitance developed between the respective top plate and the respective second plate, each capacitor comprising:
one or more layers of conductive strips forming the capacitor, wherein for each pair of neighboring conductive strips within each of the one or more layers of conductive strips:
a first conductive strip of the pair of neighboring conductive strips is coupled to the respective top plate of the capacitor and not to the respective bottom plate of the capacitor; and
a second conductive strip of the pair of neighboring conductive strips is coupled to the respective bottom plate of the capacitor and not to the respective top plate of the capacitor; and
a low-impedance conductive layer spanning an area underneath all respective one or more layers of conductive strips;
a differential amplifier comprising an input stage having a first input and a second input, wherein the first input is coupled to the respective top plate of each capacitor of a first subset of the plurality of capacitors, and wherein the second input is coupled to the respective top plate of each capacitor of a second subset of the plurality of capacitors; and
a first transistor device comprising:
a control terminal coupled to the input stage of the differential amplifier; and
a first channel terminal coupled to the low-impedance conductive layer.
2. The switched-capacitor circuit of claim 1 , wherein the first transistor device further comprises a second channel terminal coupled to a supply voltage.
3. The switched-capacitor circuit of claim 1 , wherein the first channel terminal of the first transistor device is coupled to a current source configured to source a specified current through the first transistor device.
4. The switched-capacitor circuit of claim 1 , wherein the first input of the differential amplifier is an inverting input and the second input of the differential amplifier is a non-inverting input.
5. The switched-capacitor circuit of claim 1 , wherein the input stage of the differential amplifier comprises a second transistor device and a third transistor device, wherein the first input of the differential amplifier is a control terminal of the second transistor device and the second input of the differential amplifier is a control terminal of the third transistor device;
wherein a first channel terminal of the second transistor device and a first channel terminal of the third transistor device are each coupled to the control terminal of the first transistor device.
6. The switched-capacitor circuit of claim 5 , wherein the differential amplifier is an operational transconductance amplifier, the first transistor device is an NMOS device, and the second and third transistor devices are PMOS devices.
7. The switched-capacitor circuit of claim 1 , wherein the one or more layers of conductive strips comprise metal layers.
8. The switched-capacitor circuit of claim 1 , wherein the low-impedance conductive layer comprises a polysilicon plate.
9. The switched-capacitor circuit of claim 1 , wherein the low-impedance conductive layer comprises one of:
a solid planar low-impedance conductive material; and
a plurality of low-impedance conductive strips.
10. The switched-capacitor circuit of claim 1 , wherein the low-impedance conductive layer comprises a diffusion layer configured within a substrate of the semiconductor beneath a bottom layer of the one or more layers of conductive strips.
11. The switched-capacitor circuit of claim 10 , wherein the diffusion layer comprises one of:
an n-well diffusion layer; and
a p-well diffusion layer.
12. The switched-capacitor circuit of claim 1 , wherein conductive strips of the one or more layers of conductive strips coupled to the respective top plate of the capacitor are vertically aligned.
13. The switched-capacitor circuit of claim 1 , wherein conductive strips of the one or more layers of conductive strips coupled to the respective bottom plate of the capacitor are vertically aligned.