IP Library Granted Patent US 9,160,348
Granted Patent B2
US 9,160,348 · App. 13/303,922 · Granted Oct 13, 2015

Apparatus and method to update a default time interval based on process corner, temperature and voltage

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Quick Facts
Patent No.
US 9,160,348
App. No.
13/303,922
Granted
Oct 13, 2015
Kind
B2
Abstract

A processor arrangement changes its default time interval for entering a power saving mode based on sensed operating conditions and predetermined time intervals to be used under various operating conditions to optimize power saving.

Claims (64)

1. A processor arrangement, comprising:

a processor configured to enter a power saving mode based on a default time interval;

a monitor configured to identify a process corner associated with the processor;

a memory storing a look-up table including respective time intervals associated with a plurality of operating parameters of the processor, the look-up table corresponding to the identified process corner, wherein each respective time interval stored in the look-up table is associated with a corresponding supply voltage and a corresponding temperature of the processor;

a sensor configured to sense a temperature of the processor; and

a power manager configured to:

select, based on the identified process corner and the temperature, an updated time interval from the look-up table, and

update the default time interval based on the updated time interval.

2. The processor arrangement of claim 1 , wherein the sensor is further configured to sense a supply voltage of the processor.

3. The processor arrangement of claim 1 , wherein the memory stores a plurality of look-up tables.

4. The processor arrangement of claim 3 , wherein each look-up table in the plurality of look-up tables corresponds to a different potential process corner of a plurality of potential processor corners.

5. The processor arrangement of claim 1 , wherein the power manager is further configured to:

compare the temperature to a previously sensed temperature, and

update the default time interval based on a result of the comparison.

6. A method, comprising:

identifying a process corner associated with a processor;

determining, during a first execution of a first application by the processor, a default time interval for the processor to enter into a power saving mode based on the process corner;

detecting a second execution of a second application by the processor;

detecting a change in temperature of the processor after detecting the second execution of the second application;

reading an updated default time interval from a look-up table corresponding to the process corner, wherein the look-up table includes respective time intervals associated with a plurality of operating parameters of the processor, and wherein each respective time interval stored in the look-up table is associated with a corresponding supply voltage and a corresponding temperature of the processor; and

updating the default time interval based on the updated default time interval.

7. The method of claim 6 , further comprising:

detecting a change in supply voltage of the processor.

8. The method of claim 7 , further comprising:

updating the default time interval based on the change in supply voltage.

9. The method of claim 6 , further comprising:

selecting the look-up table from a plurality of look-up tables.

10. The method of claim 9 , wherein each look-up table in the plurality of look-up tables corresponds to a different potential process corner of a plurality of potential process corners associated with the processor.

11. An apparatus, comprising:

a processor configured to enter a low power mode based on a time interval;

a memory storing a look-up table including respective durations of time associated with a plurality of operating parameters of the processor, wherein each respective duration of time stored in the look-up table is associated with a corresponding supply voltage and a corresponding temperature of the processor; and

a power manager coupled to the processor, wherein the power manager is configured to:

determine a process corner, within which the processor is operating, wherein the look-up table corresponds to the process corner,

determine a current operating condition of the processor,

select, based on the process corner and the current operating condition, a first duration of time from the look-up table, wherein the first duration of time is a duration of idle time to elapse before the processor enters the low power mode, and

update the time interval based on the first duration of time.

12. The apparatus of claim 11 , wherein the current operating condition is a current temperature of the processor.

13. The apparatus of claim 11 , wherein the current operating condition is a current supply voltage of the processor.

14. The apparatus of claim 11 , wherein the power manager is further configured to:

determine a current temperature of the processor;

determine a current supply voltage of the processor; and

update time interval based on the current temperature, current supply voltage, and the process corner.

15. The apparatus of claim 11 , wherein the low power mode is a dormant mode.

16. The apparatus of claim 11 , further comprising:

a sensor configured to sense the current operating condition.

17. The apparatus of claim 11 , further comprising:

a silicon performance monitor configured to identify the process corner, wherein the process corner is slow, typical, or fast.

18. The apparatus of claim 17 , wherein the power manager is further configured to:

compare a reported count generated by the silicon performance monitor to a reference count associated with the process corner; and

select the first duration of time based on the reported count.

19. An apparatus, comprising:

a processor configured to enter a low power mode after a duration of idle time; and

a memory storing a plurality of look-up tables, each look-up table corresponding to a different potential process corner associated with the processor, and each look-up table having a plurality of durations of idle time indexed to corresponding operating conditions; and

a power manager coupled to the processor and the memory, wherein the power manager is configured to:

determine an actual process corner for the processor from the plurality of potential process corners,

determine a first operating condition of the processor,

select a first look-up table from the plurality of look-up tables based on the actual process corner determined for the processor, and

select the duration of idle time for the processor to enter the low power mode from the plurality of durations of idle time in the selected first look-up table based on the first operating condition.

20. The apparatus of claim 19 , wherein the power manager is further configured to:

determine the first operating condition of the processor during a first execution of a first application by the processor;

detect a second execution of a second application by the processor;

determine a second operating condition of the processor during the second execution of the second application;

select a second look-up table from the plurality of look-up tables based on a difference between the first operating condition and the second operating condition; and

update the duration of idle time based on the selected second look-up table.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2011
From: JUNG, HWISUNG
To: BROADCOM CORPORATION
Reel/Frame 027396/0796 →