IP Library Granted Patent US 9,413,312
Granted Patent B2
US 9,413,312 · App. 13/304,241 · Granted Aug 9, 2016

Real-time short-circuit detection

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Quick Facts
Patent No.
US 9,413,312
App. No.
13/304,241
Granted
Aug 9, 2016
Kind
B2
Abstract

Presented are circuits and methods for providing real-time short-circuit detection, capable of detecting a short-circuit prior to occurrence of an over-limit current event. Such a circuit can be used to provide real-time short-circuit detection for a switched-mode system for a switched-mode system having a pre-driver and a power stage, and includes a reference block for generating a reference voltage according to drive signals provided by the pre-driver, and a comparator, which may be a synchronized comparator. The comparator is configured to compare the reference voltage to a switching node voltage generated in a power stage of the switched-mode system, and to produce an output enabling detection of the short-circuit in the switched-mode system.

Claims (31)

1. A circuit for a switched-mode system having a pre-driver and a power stage, the circuit comprising:

a reference circuit configured to generate a reference voltage according to drive signals from the pre-driver and a replica load; and

a comparator circuit configured to compare the reference voltage to a switching node voltage generated by the power stage to generate and output indicative of a short-circuit in the switched-mode system,

wherein the comparator is a synchronized comparator, and the circuit further includes an adaptive clock to drive the synchronized comparator.

2. The circuit of claim 1 , wherein the adaptive clock is generated according to control signals that produce a difference between the reference voltage and the switching node voltage.

3. The circuit of claim 1 , wherein the circuit is configured to enable the detection of the short-circuit prior to an occurrence of an over-limit current event in the power stage.

4. The circuit of claim 1 , wherein the reference block comprises a scaled replica of the power stage.

5. The circuit of claim 1 , wherein the switched-mode system is one of a class-D audio amplifier and a switching regulator.

6. A switched-mode system comprising:

a power stage circuit including a switching node voltage;

a pre-driver circuit configured to produce drive signals; and

a circuit including:

a reference block circuit coupled between the pre-driver and the power stage and configured to generate a reference voltage according to the drive signals and a replica load;

a synchronized comparator circuit configured to compare the reference voltage to the switching node voltage of the power stage to produce an output indicative of a short-circuit load condition of the switched-mode system; and

an adaptive clock to drive the synchronized comparator.

7. The switched-mode system of claim 6 , wherein the adaptive clock is generated according to control signals that produce a difference between the reference voltage and the switching node voltage.

8. The switched-mode system of claim 6 , wherein the circuit is configured to enable the detection of the short-circuit load condition prior to an occurrence of an over-limit current event in the power stage.

9. The switched-mode system of claim 6 , wherein the reference block comprises a scaled replica of the power stage.

10. The switched-mode system of claim 6 , wherein the switched-mode system is a class-D audio amplifier.

11. The switched-mode system of claim 6 , wherein the switched-mode system is a switching regulator.

12. A method for use by a circuit in a switched-mode system, the method comprising:

receiving drive signals from a pre-driver circuit;

obtaining a switching node voltage generated by a power stage circuit;

generating, by a reference circuit, a reference voltage using the drive signals and a replica load;

comparing the reference voltage to the switching node voltage using a comparator circuit;

outputting, by the comparator, a signal indicative of a short-circuit in the switched-mode system; and

clocking the comparator using an adaptive clock.

13. The method of claim 12 , further comprising generating the adaptive clock according to control signals that produce a difference between the reference voltage and the switching node voltage.

14. The method of claim 12 , wherein the detecting occurs prior to an occurrence of an over-current event.

15. The method of claim 12 , wherein the switched-mode system is a class-D audio amplifier.

16. The method of claim 12 , wherein the switched-mode system is a switching regulator.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2011
From: JIANG, XICHENG; CHEN, JIANLONG; ARUNACHALAM, SASI KUMAR
To: BROADCOM CORPORATION
Reel/Frame 027276/0041 →