Variable-length code decoder
View Patent ↗An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.
1. An apparatus comprising:
a processor comprising multiple functional units operative to execute executable instructions that when executed by the multiple functional units cause the multiple functional units to:
store variable length code information among a plurality of general purpose registers of the processor;
generate decoded variable length code information by decoding the at least one variable length code; and
store the decoded variable length code information among the plurality of general purpose registers, wherein the variable length code information is associated with a number of macroblocks, and
wherein the executable instructions share the general purpose registers by causing the multiple functional units to share, using the general purpose registers, information used in executing the executable instructions when the multiple functional units generate the decoded variable length code information.
2. The apparatus of claim 1 wherein the locations of the general purpose registers in memory are dynamically allocated during run-time.
3. The apparatus of claim 1 wherein the variable length code information comprises MPEG-4 variable length code information.
4. The apparatus of claim 1 , wherein the processor comprises a MIPS processor.
5. The apparatus of claim 1 , wherein the apparatus comprises an MPEG decoder.
6. The apparatus of claim 1 , wherein the processor comprises a RISC processor.
7. The apparatus of claim 1 , wherein the macroblocks are comprised of at least a luminance macroblock and a chrominance macroblock.
8. An apparatus comprising:
a processor comprising multiple functional units operative to execute executable instructions that when executed by the multiple functional units cause the multiple functional units to:
store variable length code information among a plurality of general purpose registers;
generate decoded variable length code information by decoding the at least one variable length code; and
store the decoded variable length code information among the plurality of general purpose registers,
wherein the executable instructions share the general purpose registers by causing the multiple functional units to share, using the general purpose registers, information used in executing the executable instructions when the multiple functional units generate the decoded variable length code information; and
a storage device, operatively coupled to the processor, that stores the decoded variable length data.
9. The apparatus of claim 8 wherein the locations of the general purpose registers in memory are dynamically allocated during run-time.
10. The apparatus of claim 8 wherein the variable length code information comprises MPEG-4 variable length code information.
11. The apparatus of claim 8 , wherein the processor comprises a MIPS processor.
12. The apparatus of claim 8 , wherein the apparatus comprises an MPEG decoder.
13. The apparatus of claim 8 , wherein the processor comprises a RISC processor.
14. The apparatus of claim 8 , wherein the variable length code information is associated with a number of macroblocks, and wherein the macroblocks are comprised of at least a luminance macroblock and a chrominance macroblock.