IP Library Granted Patent US 8,633,576
Granted Patent B2
US 8,633,576 · App. 13/306,203 · Granted Jan 21, 2014

Stacked chip-on-board module with edge connector

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Quick Facts
Patent No.
US 8,633,576
App. No.
13/306,203
Granted
Jan 21, 2014
Kind
B2
Abstract

A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto.

Claims (25)

1. A module, comprising:

a module card having first and second opposed surfaces, each extending in a first direction and a second direction transverse to the first direction, and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces configured to mate with corresponding contacts of a socket, the module card having first and second apertures each extending between the first and second surfaces;

first and second microelectronic elements, the first microelectronic element having a first surface facing the first surface of the module card and a second surface opposite therefrom, the first microelectronic element having a lateral edge extending between the first and second surfaces thereof and extending in the second direction, the second microelectronic element having a front surface facing the first surface of the module card, the front surface of the second microelectronic element facing and partially overlying the second surface of the first microelectronic element and attached thereto, the front surface of the second microelectronic element projecting in the first direction beyond the lateral edge of the first microelectronic element, chip contacts of the first microelectronic element being exposed at the first surface of the first microelectronic element, chip contacts of the second microelectronic element being exposed at the front surface of the second microelectronic element and disposed beyond the lateral edge of the first microelectronic element,

the second microelectronic element having first and second opposed edges extending between the front and rear surfaces of the second microelectronic element and extending in the second direction, the front surface of the second microelectronic element having a first outer region adjacent the first edge, a second outer region adjacent the second edge, and a central region disposed between the first and second outer regions, each of the first and second outer regions and the central region having equal width such that the central region extends a middle third of a distance between the first and second edges, the chip contacts of the second microelectronic element being disposed in the central region; and

first wire bonds extending through the first aperture and coupled to the chip contacts of the first microelectronic element, and second wire bonds extending through the second aperture and coupled to the chip contacts of the second microelectronic element, wherein the edge contacts are coupled to the first and second microelectronic elements through the first and second wire bonds.

2. A module as claimed in claim 1 , wherein the first microelectronic element has a second edge opposed to the lateral edge, the first surface of the first microelectronic element and the lateral and second edges of the first microelectronic element being such that:

the first surface has a first outer region adjacent the lateral edge of the first microelectronic element, a second outer region adjacent the second edge of the first microelectronic element, and a central region disposed between the first and second outer regions of the first surface of the first microelectronic element, each of the first and second outer regions and the central region having equal width such that the central region of the first microelectronic element extends a middle third of a distance between the lateral and second edges, wherein the chip contacts of the first microelectronic element are disposed in such central region.

3. A module as claimed in claim 1 , wherein the edge contacts are exposed at at least one of the first or second surfaces of the module card.

4. A module as claimed in claim 1 , wherein at least one of the first and second microelectronic elements includes a memory storage element.

5. A module as claimed in claim 4 , further comprising a plurality of leads extending from chip contacts of the at least one of the first and second microelectronic elements to the edge contacts, wherein the leads are configured to carry an address signal usable to address the memory storage element in at least one of the first and second microelectronic elements.

6. A module as claimed in claim 1 ,

further comprising a plurality of third microelectronic elements, each third microelectronic element being electrically coupled with the module card.

7. A module as claimed in claim 6 , wherein the plurality of third microelectronic elements are arranged in a stacked configuration, each of the third microelectronic elements having a front or rear surface confronting a front or rear surface of an adjacent one of the third microelectronic elements.

8. A module as claimed in claim 6 , wherein the plurality of third microelectronic elements are arranged in a planar configuration, each of the third microelectronic elements having a peripheral surface confronting a peripheral surface of an adjacent one of the third microelectronic elements.

9. A module as claimed in claim 6 , wherein the second microelectronic element includes volatile RAM, the third microelectronic elements each include nonvolatile memory, and the first microelectronic element includes a processor configured to predominantly control transfers of data between an external component and the second and third microelectronic elements.

10. A module as claimed in claim 6 , wherein the second microelectronic element includes a volatile frame buffer memory storage element, the third microelectronic elements each include nonvolatile memory, and the first microelectronic element includes a graphics processor.

11. A module as claimed in claim 1 , wherein each of the first and second microelectronic elements is a semiconductor chip.

12. A module, comprising:

a module card having a first surface, a second surface opposite from the first surface, and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces configured to mate with corresponding contacts of a socket; and

first and second microelectronic elements having front surfaces facing the first surface of the module card, each microelectronic element being electrically coupled with the module card, the front surface of the first microelectronic element facing the first surface of the module card, the front surface of the second microelectronic element partially overlying a rear surface of the first microelectronic element and attached thereto, the front surface of the second microelectronic element projecting in the first direction beyond a lateral edge of the first microelectronic element, chip contacts of the second microelectronic element being exposed at the front surface of the second microelectronic element and disposed beyond the lateral edge of the first microelectronic element,

the second microelectronic element having first and second opposed edges extending between the front and rear surfaces of the second microelectronic element, the front surface of the second microelectronic element having a first outer region adjacent the first edge, a second outer region adjacent the second edge, and a central region disposed between the first and second outer regions, each of the first and second outer regions and the central region having equal width such that the central region extends a middle third of a distance between the first and second edges, the chip contacts of the second microelectronic element being disposed in the central region; and

a plurality of first leads electrically coupled to chip contacts on the front surface of the first microelectronic element and to the edge contacts, and a plurality of second leads electrically coupled to the chip contacts of the second microelectronic element and to the edge contacts,

wherein the module card further includes first and second apertures extending between the first and second surfaces, the first aperture aligned with the chip contacts of the first microelectronic element, and the second aperture aligned with the chip contacts of the second microelectronic element,

wherein the first leads include first lead bonds extending from conductive elements on the module card to the chip contacts of the first microelectronic element, and the second leads include second lead bonds extending from the conductive elements to the chip contacts of the second microelectronic element.

13. A module as claimed in claim 12 , wherein the chip contacts of the first microelectronic element are not aligned with the second aperture, and wherein the chip contacts of the second microelectronic element are not aligned with the first aperture.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2012
From: ZOHNI, WAEL; HABA, BELGACEM
To: TESSERA, INC.
Reel/Frame 027841/0462 →