Time-interleaved analog-to-digital converter bandwidth matching

1. A time-interleaved Analog-to-Digital Converter (ADC) comprising:

a set of sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit;

wherein each sample-and-hold circuit comprises:

a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of said switch, said switch for switching between a sample mode and a hold mode; and

a capacitor bank associated with said bootstrap circuit such that a setting of said capacitor bank affects an ON state intrinsic resistance of said switch by affecting said voltage level.

2. The ADC of claim 1 , wherein said capacitor bank is configured to be set after testing said ADC to adjust said frequency response of said sample-and-hold circuit.

3. The ADC of claim 1 , further comprising a memory coupled to said capacitor bank, said memory configured to store a setting of said capacitor bank.

4. The ADC of claim 1 , wherein said memory comprises a one-time programmable memory.

5. The ADC of claim 1 , wherein said capacitor bank is connected between a control signal and ground, said control signal being between said bootstrap circuit and said gate terminal.

6. The ADC of claim 5 , wherein said capacitor bank is connected in parallel to a main capacitor of said bootstrap circuit.

7. The ADC of claim 1 , wherein said capacitor bank comprises a binary weighted capacitor bank.

8. A method for matching bandwidths within a time-interleaved Analog-to-Digital Converter (ADC), the method comprising:

determining a frequency response of a sample-and-hold circuit for each of a set of sub-ADC circuits within a time-interleaved ADC;

adjusting a bandwidth of at least one of said sub-ADC circuits by adjusting an efficiency of a bootstrap circuit associated with a sample-and-hold circuit of said at least one of said sub-ADC circuits, said adjusting causing bandwidths among said sub-ADC circuits to be more closely matched.

9. The method of claim 8 , wherein adjusting said efficiency comprises adjusting a capacitive trim load.

10. The method of claim 9 , wherein said capacitive trim load is placed in parallel to a main bootstrap capacitor of said sample-and-hold circuit of said at least one of said sub-ADC circuits to increase said bandwidth of said at least one sub-ADC circuit.

11. The method of claim 9 , wherein said capacitive trim load is placed between a gate terminal of a switch of said sample-and-hold circuit of said at least one of said sub-ADC circuits and ground to increase said bandwidth of said at least one sub-ADC circuit.

12. The method of claim 9 , wherein said capacitive trim load comprises a capacitor bank.

13. The method of claim 12 , wherein said capacitor bank comprises a binary weighted capacitor bank.

14. The method of claim 12 , further comprising, storing a setting of said capacitor bank setting into a memory associated with said capacitor bank.

15. The method of claim 8 , further comprising, increasing a bandwidth of each of said sub-ADC circuits to match a bandwidth of the sub-ADC circuit within said time-interleaved ADC having the highest bandwidth.

16. The method of claim 8 , further comprising, decreasing a bandwidth of each of said sub-ADC circuits to match a bandwidth of the sub-ADC circuit within said time-interleaved ADC having the smallest bandwidth.

17. A time-interleaved Analog-to-Digital Converter (ADC) comprising:

a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit;

wherein each sample-and-hold circuit comprises:

a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of said switch, said switch for switching between a sample mode and a hold mode; and

a capacitor bank associated with said bootstrap circuit such that a setting of said capacitor bank affects an intrinsic resistance of said switch by adjusting said voltage level;

wherein, said capacitor bank is configured to be set to a value that will adjust a frequency response of said sample-and-hold circuit to a predetermined bandwidth.

18. The ADC of claim 17 , further comprising a memory coupled to said capacitor bank, said memory configured to store a setting of said capacitor bank.

19. The ADC of claim 18 , wherein said memory comprises a one-time programmable memory.

20. The ADC of claim 17 , wherein said capacitor bank comprises a binary weighted capacitor bank.