Manufacturing method of thin film transistor array panel
View Patent ↗A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.
1. A method for manufacturing a thin film transistor array panel, comprising:
depositing a first metal layer on a substrate;
depositing a second metal layer on the first metal layer;
forming a first photosensitive pattern on the second metal layer;
simultaneously etching the first metal layer and the second metal layer with a non-peroxide-based first etchant, using the first photosensitive pattern as a mask;
removing a portion of the first photosensitive pattern to form a second photosensitive pattern; and
etching the second metal layer with a non-peroxide-based second etchant, using the second photosensitive pattern as a mask, to form a gate conductor and a first electrode on the substrate;
forming a gate insulating layer on the gate conductor and the first electrode;
forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer;
forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and
forming a second electrode on the passivation layer.
2. The method of claim 1 , wherein the first etchant comprises ammonium persulfate (APS), nitric acid, ammonium fluoride (AF), aminotetrazole (ATZ), or fluoroboric acid (FBA).
3. The method of claim 2 , wherein the second etchant comprises ammonium per sulfate (APS), nitric acid, aminotetrazole (ATZ), or ammonium acetate (AA).
4. The method of claim 3 , wherein the first electrode is a reference electrode and the second electrode is a pixel electrode.
5. The method of claim 3 , wherein the first electrode is a pixel electrode and the second electrode is a reference electrode.
6. The method of claim 1 , wherein the first electrode is a reference electrode and the second electrode is a pixel electrode.
7. A method for manufacturing a thin film transistor array panel, comprising:
simultaneously forming a gate conductor and a pixel electrode on a substrate, using a first non-peroxide-based etchant;
forming a gate insulating layer on the gate conductor and the first electrode;
forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer;
forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and
forming a reference electrode on the passivation layer.
8. A method for manufacturing a thin film transistor array panel, comprising:
forming a first metal layer on a substrate;
forming a second metal layer on the first metal layer;
forming a first photosensitive pattern and a second photosensitive pattern on the second metal layer;
simultaneously etching the first and second metal layers with a non-peroxide based first etchant, using the first and second photosensitive pattern as a mask;
performing an etch-back process to remove the first photosensitive pattern and to reduce the thickness of the second photosensitive pattern, thereby forming a third photosensitive pattern; and
etching the second metal layer with a non-peroxide-based second etchant, using the third photosensitive pattern as a mask, thereby forming a gate conductor and a first electrode;
forming a gate insulating layer on the gate conductor and the first electrode;
forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer;
forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and
forming a second electrode on the passivation layer.
9. The method of claim 8 , wherein the first film pattern is thinner than the second film pattern.
10. The method of claim 8 , wherein:
the first etchant comprises ammonium persulfate (APS), nitric acid, ammonium fluoride (AF), aminotetrazole (ATZ), or fluoroboric acid (FBA); and
the second etchant comprises ammonium per sulfate (APS), nitric acid, aminotetrazole (ATZ), or ammonium acetate (AA).
11. The method of claim 8 , wherein:
the first metal layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO); and
the second metal layer comprises copper or a copper alloy.
12. The method of claim 8 , wherein: the first and second electrodes are different ones of a reference electrode and a pixel electrode.