Data processing device
A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
1. A data processing device to be mounted on a printed circuit board on which a first memory device having a first inversion data strobe signal circuit terminal and a first non-inversion data strobe signal circuit terminal is mounted, wherein
the data processing device includes a package having an upper surface and a lower surface opposite to the upper surface, a microcomputer chip having a first inversion data strobe signal circuit and a first non-inversion data strobe signal circuit, and mounted on the upper surface of the package, and a plurality of ball electrodes formed on the lower surface of the package;
a shape in a plan view of the package is comprised of a quadrangle having a first side;
a shape in the plan view of the microcomputer chip is comprised of a quadrangle having a second side;
the microcomputer chip is mounted on the upper surface of the package such that the second side of the microcomputer chip is arranged side by side with the first side of the package in the plan view;
both the first inversion data strobe signal circuit and the first non-inversion data strobe signal circuit of the microcomputer chip are arranged along the second side of the microcomputer chip;
the ball electrodes are arranged along the first side of the package and arranged in plural rows;
a first non-inversion data strobe signal circuit ball electrode of the ball electrodes electrically connected with the first non-inversion data strobe signal circuit of the microcomputer chip via a first wiring line formed in the package, and electrically connected with the first non-inversion data strobe signal circuit terminal of the first memory device is arranged along a direction intersecting with the first side of the package in the plan view, and is arranged side by side with a first inversion data strobe signal circuit ball electrode of the ball electrodes electrically connected with the first inversion data strobe signal circuit of the microcomputer chip via a second wiring line formed in the package, and electrically connected with the first inversion data strobe signal circuit terminal of the first memory device; and
the first inversion data strobe signal circuit ball electrode and the first non-inversion data strobe signal circuit ball electrode are disposed at first and second rows from the first side of the package, or third and fourth rows from the first side of the package, respectively.
2. The data processing device according to claim 1 , wherein the first memory device has a first upper byte inversion data strobe signal circuit terminal, a first upper byte non-inversion data strobe signal circuit terminal, a second lower byte inversion data strobe signal circuit terminal, and a second lower byte non-inversion data strobe signal circuit terminal;
wherein the microcomputer chip has a first upper byte inversion data strobe signal circuit, a first upper byte non-inversion data strobe signal circuit, a second lower byte inversion data strobe signal circuit, and a second lower byte non-inversion data strobe signal circuit; and
wherein a second non-inversion data strobe signal circuit ball electrode of the ball electrodes electrically connected with the second lower byte non-inversion data strobe signal circuit of the microcomputer chip via a third wiring line formed in the package, and electrically connected with the second lower byte non-inversion data strobe signal circuit terminal of the first memory device is arranged side by side with a second inversion data strobe signal circuit ball electrode of the ball electrodes electrically connected with the second lower byte inversion data strobe signal circuit of the microcomputer chip via a fourth wiring line formed in the package, and electrically connected with the second lower byte inversion data strobe signal circuit terminal of the first memory device.
3. The data processing device according to claim 2 , wherein the second inversion data strobe signal circuit ball electrode and the second non-inversion data strobe signal circuit ball electrode are disposed at first and second rows from the first side of the package, or third and fourth rows from the first side of the package, respectively.
4. The data processing device according to claim 3 , wherein the first inversion data strobe signal circuit ball electrode is electrically connected with the first inversion data strobe signal circuit terminal via a first differential signal line formed in a first wiring layer of the printed circuit board;
wherein the first non-inversion data strobe signal circuit ball electrode is electrically connected with the first non-inversion data strobe signal circuit terminal via a second differential signal line formed in the first wiring layer of the printed circuit board and arranged next to the first differential signal line;
wherein the second inversion data strobe signal circuit ball electrode is electrically connected with the second lower byte inversion data strobe signal circuit terminal via a third differential signal line formed in the first wiring layer of the printed circuit board; and
wherein the second non-inversion data strobe signal circuit ball electrode is electrically connected with the second lower byte non-inversion data strobe signal circuit terminal via a fourth differential signal line formed in the first wiring layer of the printed circuit board and arranged next to the third differential signal line.
5. The data processing device according to claim 4 , wherein a second memory device having a third upper byte inversion data strobe signal circuit terminal, a third upper byte non-inversion data strobe signal circuit terminal, a fourth lower byte inversion data strobe signal circuit terminal and a fourth lower byte non-inversion data strobe signal circuit terminal is mounted on the printed circuit board;
wherein the microcomputer chip has a third upper byte inversion data strobe signal circuit, a third upper byte non-inversion data strobe signal circuit, a fourth lower byte inversion data strobe signal circuit, and a fourth lower byte non-inversion data strobe signal circuit;
wherein a third non-inversion data strobe signal circuit ball electrode of the ball electrodes electrically connected with the third upper byte non-inversion data strobe signal circuit of the microcomputer chip via a fifth wiring line formed in the package, and electrically connected with the third upper byte non-inversion data strobe signal circuit terminal of the second memory device is arranged side by side with a second inversion data strobe signal circuit ball electrode of the ball electrodes electrically connected with the third upper byte inversion data strobe signal circuit of the microcomputer chip via a sixth wiring line formed in the package, and electrically connected with the third upper byte inversion data strobe signal circuit terminal of the second memory device; and
wherein a fourth non-inversion data strobe signal circuit ball electrode of the ball electrodes electrically connected with the fourth lower byte non-inversion data strobe signal circuit of the microcomputer chip via a seventh wiring line formed in the package, and electrically connected with the fourth lower byte non-inversion data strobe signal circuit terminal of the second memory device is arranged side by side with a fourth inversion data strobe signal circuit ball electrode of the ball electrodes electrically connected with the fourth lower byte inversion data strobe signal circuit of the microcomputer chip via a sixth wiring line formed in the package, and electrically connected with the fourth lower byte inversion data strobe signal circuit terminal of the second memory device.