Boosting memory module performance
View Patent ↗Power supplied to a memory module is provided. A first voltage is supplied to a first power distribution pathway, the first voltage being from a voltage supplied to a printed circuit board on which the memory module resides. A second voltage is generated, the second voltage being generated by a voltage regulator. The second voltage is supplied to a second power distribution pathway.
1. A memory sub-system of at least one memory module, comprising:
a first power distribution pathway configured to receive a first voltage level from a voltage source coupled to a printed circuit board on which the at least one memory module resides;
a voltage regulator configured to receive the first voltage level and operable to generate a second voltage level, the second voltage level being higher than the first voltage level; and
a second power distribution pathway configured to receive the second voltage level from the voltage regulator, wherein the second power distribution pathway is further configured to provide a core voltage to each of a plurality of memory devices on the at least one memory module.
2. The memory sub-system of claim 1 , wherein the voltage regulator is housed on the at least one memory module.
3. The memory sub-system of claim 1 , wherein the voltage regulator is configured to receive the first voltage level from the voltage source coupled to the printed circuit board.
4. The memory sub-system of claim 1 , wherein the first power distribution pathway is further configured to operate I/O structures on each of a plurality of memory devices on the at least one memory module.
5. The memory sub-system of claim 1 , wherein the voltage regulator is configured to receive a third voltage from an external voltage source, wherein the external voltage source is external to the at least one memory module.
6. The memory sub-system of claim 5 , wherein the voltage regulator is a step down voltage regulator configured to generate the second voltage level by decreasing the third voltage level received from the external voltage source.
7. The memory sub-system of claim 1 , wherein the voltage regulator is a step up voltage regulator configured to generate the second voltage level by increasing the received first voltage level.
8. The memory sub-system of claim 1 , wherein the voltage regulator includes comparing circuitry to compare the first voltage level and the second voltage level and determine a voltage difference.
9. The memory sub-system of claim 8 , wherein the comparing circuitry is enabled to force a predetermined voltage difference between the first voltage level and the second voltage level.
10. The memory sub-system of claim 1 , further comprising at least one switch coupled to the voltage regulator and configured to program the voltage regulator to generate, as the second voltage level, a voltage from a range of voltage levels.
11. The memory sub-system of claim 1 , further comprising a microcontroller coupled to the voltage regulator, the microcontroller being configured to control the level of voltage generated by the voltage regulator.
12. The memory sub-system of claim 11 , further comprising a switch coupled to the microcontroller, and configured to program the microcontroller based on whether the switch is enabled or disabled.
13. The memory sub-system of claim 11 , further comprising an external interface coupled to the microcontroller, the external interface configured to program the microcontroller in response to voltage input data received by the external interface.
14. A method of supplying power to at least one memory module, comprising:
supplying a first voltage to a first power distribution pathway, the first voltage being from a voltage supplied to a printed circuit board on which the at least one memory module resides;
generating a second voltage, the second voltage being generated by a voltage regulator; and
supplying the second voltage to a second power distribution pathway, wherein the second power distribution pathway is configured to provide a core voltage to each of a plurality of memory devices on the at least one memory module.
15. The method of claim 14 , wherein the voltage regulator is housed on the at least one memory module.
16. The method of claim 14 , wherein the voltage regulator is associated with the first power distribution pathway.
17. The method of claim 14 , wherein the first power distribution pathway is further configured to operate I/O structures on each of a plurality of memory devices on the at least one memory module.
18. The method of claim 14 , wherein the voltage regulator is configured receive a third voltage from an external voltage source, and wherein the external voltage source is external to the at least one memory module.
19. The method of claim 18 , wherein the voltage regulator is a step down voltage regulator configured to generate the second voltage level by decreasing the third voltage level received from the external voltage source.
20. The method of claim 14 , wherein the voltage regulator is a step up voltage regulator configured to generate the second voltage level by increasing the received first voltage level.
21. The method of claim 14 , wherein the voltage regulator includes comparing circuitry to compare the first voltage level and the second voltage level and determine a voltage difference.
22. The method of claim 21 , wherein the comparing circuitry is enabled to force a predetermined voltage difference between the first voltage level and the second voltage level.
23. The method of claim 14 , further comprising programming the voltage regulator to generate, as the second voltage level, a voltage from a range of voltages via at least one switch.
24. The method of claim 14 , further comprising controlling the level of voltage generated by the voltage regulator via a microcontroller.
25. The method of claim 24 , further comprising programming the microcontroller based on whether a switch associated with the microcontroller is enabled or disabled.
26. The method of claim 24 , further programming the microcontroller in response to voltage input data received by an external interface associated with the microcontroller.