IP Library Granted Patent US 8,291,128
Granted Patent B2
US 8,291,128 · App. 13/311,150 · Granted Oct 16, 2012

Systems configured to identify an operating mode

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,291,128
App. No.
13/311,150
Granted
Oct 16, 2012
Kind
B2
Abstract

Systems having a host computer system, a memory device coupled to the host computer system, and identification circuitry. The identification circuitry is configured to identify an operating mode of the host computer system from comparing applied signals to sensed signals.

Claims (37)

1. A system, comprising:

a host computer system;

identification circuitry; and

a memory device coupled to the host computer system;

wherein the identification circuitry is configured to identify an operating mode of the host computer system from a plurality of signals sensed at an interface between the host computer system and the memory device in response to a plurality of signals previously applied to the interface.

2. The memory device of claim 1 , further comprising:

a controller coupled to the identification circuitry, wherein the controller is operable to configure the memory device to the identified operating mode responsive to the identification circuitry.

3. The memory device of claim 2 , wherein the controller is operable to configure the memory device to a preliminary operating mode before the identification circuitry identifies the operating mode of the host computer system.

4. The memory device of claim 1 , wherein the identification circuitry comprises encoding circuitry and sensing circuitry.

5. The memory device of claim 1 , wherein the memory device comprises a flash memory card.

6. The memory device of claim 1 , wherein the identification circuitry is physically formed on the memory device.

7. The memory device of claim 1 , wherein the identification circuitry is physically formed in an adapter module coupled between the host computer system and the memory device.

8. The memory device of claim 1 , wherein the identification circuitry is configured to identify a first operating mode if a particular signal from the host computer system has a particular value and to identify a different operating mode if the particular signal from the host computer system has a value different than the particular value.

9. A system, comprising:

a host computer system; and

a memory device coupled to the host computer system, the memory device comprising:

a memory module;

an interface comprising a plurality of terminals for communication with the host computer system;

identification circuitry configured to generate and to decode one or more defined sets of signals where each set of signals corresponds to a particular operating mode of the host computer system; and

a controller coupled to the memory module and the interface wherein the controller is operable to sequentially apply the sets of signals to the plurality of terminals of the interface, to configure the memory device to a particular operating mode corresponding to an applied set of signals in response to a set of signals sensed at the plurality of terminals of the interface matching the set of signals applied to the plurality of terminals of the interface, and to configure the memory device to a default operating mode if no set of signals sensed at the plurality of terminals of the interface match any of the sets of signals applied to the plurality of terminals of the interface.

10. The system of claim 9 , wherein the controller is further operable to apply each of the sets of signals to terminals of the interface that are inactive for the operating mode corresponding to the set of signals being applied.

11. The system of claim 9 , wherein the controller is further operable to configure the memory device to operate in a preliminary operating mode before sequentially applying the sets of signals to the plurality of terminals of the interface.

12. The system of claim 9 , wherein the controller is further operable to configure the memory device to operate in a defined operating mode without sequentially applying the sets of signals to the plurality of terminals of the interface if a defined condition is met during power-up of the memory device.

13. The system of claim 9 , wherein each set of signals of the defined sets of signals is different from other sets of signals of the defined sets of signals.

14. A system, comprising:

a host computer system;

a memory device coupled to the host computer system;

identification circuitry, wherein the identification circuitry is configured to generate a first set of signals to be applied to signals originating from the host computer system, and to sense a second set of signals from the signals originating from the host computer system after the application of the first set of signals; and

a controller, wherein the controller is operable to configure the memory device to a particular operating mode when the second set of signals match the first set of signals.

15. The system of claim 14 , wherein the first set of signals corresponds to a particular predetermined code of a plurality of predetermined codes, each predetermined code corresponding to a particular operating mode of the host computer system.

16. The system of claim 14 , wherein memory device comprises the controller and the identification circuitry.

17. The system of claim 14 , wherein the controller is further operable to configure the memory device to a preliminary operating mode before the identification circuitry applies the first set of signals to the signals originating from the host computer system.

18. The system of claim 14 , wherein the controller is further operable to configure the memory device to operate in a defined operating mode without applying the first set of signals to the signals originating from the host computer system if a defined condition is met during power-up of the memory device.

19. The system of claim 14 , further comprising:

wherein the identification circuitry is further configured to generate a third set of signals to be applied to the signals originating from the host computer system if the second set of signals differ from the first set of signals, and to sense a fourth set of signals from the signals originating from the host computer system after the application of the third set of signals; and

wherein the controller is further operable to configure the memory device to an operating mode different than the particular operating mode if the fourth set of signals matches the third set of signals.

20. The system of claim 19 , wherein the controller is further operable to configure the memory device to a default operating mode if no applied set of signals matches a corresponding sensed set of signals.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
MERGER Recorded Jun 11, 2013
From: LEXAR MEDIA, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030591/0277 →