Method and apparatus for timing adjustment
View Patent ↗A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
1. A data latch timing adjustment method for
receiving an external strobe signal and external data in synchronism with the external strobe signal,
the method comprising:
a system latch timing adjustment step of
receiving check data in synchronism with the external strobe signal and
performing a phase adjustment between the external strobe signal and the system clock so that the external data is properly latched with the system clock.
2. The data latch timing adjustment method of claim 1 , wherein in the system latch timing adjustment step:
the strobe signal is delayed to adjust the system clock with a plurality of delay amounts.
3. The data latch timing adjustment method of claim 1 , wherein in the system latch timing adjustment step:
the check data is produced in synchronism with each delayed strobe signal.
4. The data latch timing adjustment method of claim 1 , wherein the system latch timing adjustment step is performed in response to a mode select signal.
5. The data latch timing adjustment method of claim 1 , wherein the system clock is generated by PLL circuit.
6. A data latch timing adjustment method for
receiving an external strobe signal and external data in synchronism with the external strobe signal,
the method comprising:
a strobe latch timing adjustment step of
performing a phase adjustment between the external strobe signal and the external data so that the external data is properly latched with the external strobe signal.
7. The data latch timing adjustment method of claim 6 , wherein in the strobe latch timing adjustment step:
the data signal is delayed to adjust the strobe signal with a plurality of delay amounts.
8. The data latch timing adjustment method of claim 6 , wherein the strobe signal is input from a memory to a data latch timing adjustment apparatus.
9. The data latch timing adjustment method of claim 6 , wherein the strobe latch timing adjustment step is performed in response to a mode select signal.
10. The data latch timing adjustment method of claim 6 , wherein the system clock is generated by PLL circuit.
11. A data latch timing adjustment apparatus for
receiving an external strobe signal and external data in synchronism with the external strobe signal,
the apparatus comprising:
a system latch timing adjustment circuit being operable
to receive check data in synchronism with the external strobe signal and
to perform a phase adjustment between the external strobe signal and the system clock so that the external data is properly latched with the system clock.
12. The data latch timing adjustment apparatus of claim 11 , wherein in the system latch timing adjustment circuit:
the strobe signal is delayed to adjust the system clock with a plurality of delay amounts.
13. The data latch timing adjustment apparatus of claim 11 , wherein in the system latch timing adjustment circuit:
the check data is produced in synchronism with each delayed strobe signal.
14. The data latch timing adjustment apparatus of claim 11 , wherein the system latch timing adjustment circuit is operable in response to a mode select signal.
15. The data latch timing adjustment apparatus of claim 11 , wherein the system clock is generated by PLL circuit.
16. A data latch timing apparatus for
receive an external strobe signal and external data in synchronism with the external strobe signal,
the apparatus comprising:
a strobe latch timing adjustment circuit being operable
to perform a phase adjustment between the external strobe signal and the external data so that the external data is properly latched with the external strobe signal.
17. The data latch timing adjustment apparatus of claim 16 , wherein in the strobe latch timing adjustment circuit:
the data signal is delayed to adjust the strobe signal with a plurality of delay amounts.
18. The data latch timing adjustment apparatus of claim 16 , wherein the strobe signal is input from a memory to a data latch timing adjustment apparatus.
19. The data latch timing adjustment apparatus of claim 16 , wherein the strobe latch timing adjustment circuit is operable in response to a mode select signal.
20. The data latch timing adjustment apparatus of claim 16 , wherein the system clock is generated by PLL circuit.