Methods and apparatus for finFET SRAM arrays in integrated circuits

1. An integrated circuit, comprising:

a first single port SRAM array of a plurality of first bit cells arranged in rows and columns, each bit cell having a y pitch of distance Y 1 and an x pitch of distance X 1 , the ratio of X 1 to Y 1 being greater than or equal to 2, each of the plurality of bit cells forming a 6T SRAM cell of single fin finFET transistors and each of the first bit cells receiving a cell positive voltage supply CVdd from a first voltage control circuit; and

a second single port SRAM array of a plurality of second bit cells arranged in rows and columns, each second bit cell having a y pitch of distance Y 2 and an x pitch of distance X 2 , the ratio of X 2 to Y 2 being greater than or equal to 3, each of the plurality of second bit cells further comprising a 6T SRAM cell including multiple fin finFET transistors and each of the second bit cells receiving a second cell positive voltage supply CVdd from a second voltage control circuit;

wherein the ratio of X 2 to X 1 is greater than about 1.1.

2. The integrated circuit of claim 1 , wherein the first bit cells each further comprise:

two inverters cross coupled between a storage node and a complementary storage node, each of the two inverters comprising a single fin finFET pull up transistor coupled between the cell positive voltage supply CVdd and the corresponding one of the storage nodes and a single fin finFET pull down transistor coupled between the respective one of the storage nodes and a cell negative voltage supply CVss; and

a pair of pass gates coupled between a respective one of a bit line and a complementary bit line and a corresponding one of the storage node and the complementary storage node, each pass gate comprising a single fin finFET transistor with a gate terminal coupled to a word line;

wherein the cell positive voltage supply CVdd is connected to the first voltage control circuit; and

wherein the second bit cells each further comprise:

two inverters cross coupled between a storage node and a complementary storage node, each of the two inverters comprising a single fin finFET pull up transistor coupled between the second cell positive voltage supply CVdd and one of the storage nodes and a multiple fin finFET pull down transistor coupled between the respective one of the storage nodes and a cell negative voltage supply CVss; and

a pair of pass gates coupled between a respective one of a bit line and a complementary bit line and a corresponding one of the storage node and the complementary storage node, each pass gate further comprising a multiple fin finFET transistor with a gate coupled to a word line.

3. The integrated circuit of claim 2 , wherein the first voltage control circuit is a write assist circuit comprising an input coupled to a periphery Vdd power line, an output coupled to the cell positive voltage supply CVdd, and an enable input, the enable input having a read state indicating a read cycle and a write state indicating a write cycle.

4. The integrated circuit of claim 3 wherein during the write cycle, the first voltage control circuit outputs a CVdd voltage lower than the periphery Vdd power line.

5. The integrated circuit of claim 3 wherein during the read cycle, the first voltage control circuit outputs a CVdd voltage equal to or higher than the periphery Vdd power line.

6. The integrated circuit of claim 3 wherein the first voltage control circuit further comprises a standby mode circuit, and outputs a CVdd voltage lower than the periphery Vdd power line responsive to a standby mode input.

7. The integrated circuit of claim 3 , wherein during a write cycle a word line voltage to the cells is equal to the periphery Vdd voltage, and the first voltage control circuit outputs a CVdd voltage than is lower than the word line voltage by at least 50 millivolts.

8. The integrated circuit of claim 1 wherein the first single port SRAM array has a voltage control circuit for each column of first bit cells.

9. The integrated circuit of claim 2 wherein for each of the first bit cells, the pull up transistors are p-type transistors in an n-well, and each of the first bit cells further comprise an n-well connection that is electrically isolated from the cell positive voltage supply CVdd.

10. An integrated circuit, comprising:

a first single port SRAM array of a plurality of first bit cells arranged in rows and columns, each bit cell having a y pitch of distance Y 1 and an x pitch of distance X 1 , the ratio of X 1 to Y 1 being greater than or equal to 2, each of the plurality of bit cells forming a 6T SRAM cell of single fin finFET transistors and each of the first bit cells receiving a cell positive voltage supply CVdd from a first voltage control circuit; and

a second single port SRAM array of a plurality of second bit cells arranged in rows and columns, each second bit cell having a y pitch of distance Y 2 and an x pitch of distance X 2 , the ratio of X 2 to Y 2 being greater than or equal to 3, each of the plurality of second bit cells further comprising a 6T SRAM cell including multiple fin finFET transistors and each of the second bit cells receiving a second cell positive voltage supply CVdd from a predetermined Vdd voltage supply;

wherein the ratio of X 2 to X 1 is greater than about 1.1.

11. The integrated circuit of claim 10 , wherein the first bit cells each further comprise:

two inverters cross coupled between a storage node and a complementary storage node, each of the two inverters comprising a single fin finFET pull up transistor coupled between the cell positive voltage supply CVdd and the corresponding one of the storage nodes, and a single fin finFET pull down transistor coupled between the respective one of the storage nodes and a cell negative voltage supply CVss; and

a pair of pass gates coupled between a respective one of a bit line and a complementary bit line and a corresponding one of the storage node and the complementary storage node, each pass gate comprising a single fin finFET transistor with a gate terminal coupled to a word line;

wherein the second bit cells each further comprise two inverters cross coupled between a storage node and a complementary storage node, each of the two inverters comprising a single fin finFET pull up transistor coupled between the second cell positive voltage supply CVdd and one of the storage nodes, and a multiple fin finFET pull down transistor coupled between the respective one of the storage nodes and a cell negative voltage supply CVss, and a pair of pass gates coupled between a respective one of a bit line and a complementary bit line and a corresponding one of the storage node and the complementary storage node, each pass gate further comprising a multiple fin finFET transistor with a gate coupled to a word line.

12. The integrated circuit of claim 11 wherein the first voltage control circuit further comprises a voltage input node coupled to a Vdd supply input, an output coupled to the cell positive voltage supply CVdd, and an enable input having a read state indicating a read cycle, a write state indicating a write cycle, and a standby state indicating a standby mode.

13. The integrated circuit of claim 12 wherein during a write cycle, the first voltage control circuit outputs a CVdd voltage lower than the Vdd supply input.

14. The integrated circuit of claim 12 wherein during a read cycle the first voltage control circuit outputs a CVdd voltage higher than the Vdd supply input.

15. The integrated circuit of claim 12 , wherein during a write cycle, the word lines are at a voltage substantially equal to the Vdd supply input, and the first voltage control circuit outputs a voltage lower than the word line voltage by between 50 and 400 millivolts.

16. The integrated circuit of claim 10 and further comprising a third SRAM array, the third SRAM array comprising a plurality of third size bit cells, the third size bit cells each comprising:

two cross coupled inverters coupled to store data at a storage node and a complementary storage node, each of the cross coupled inverters comprising a p-type single fin finFET pull up transistor coupled between a cell positive supply voltage CVdd and a respective one of the storage node and the complementary storage node, an n-type single fin finFET pull down transistor coupled between a respective one of the storage node and the complementary storage node and a first cell negative supply voltage CVss;

two write pass gates each comprising a single fin finFET transistor having a gate coupled to a word line and coupling a respective one of a write bit line and a complementary write bit line to the corresponding storage node and complementary storage node; and

a read port comprising a read pass gate and a read pull down transistor coupled in series between a read bit line and a second cell negative supply voltage CVss, each of the read pass gate and read pull down transistors comprising a multiple fin finFET device.

17. The integrated circuit of claim 1 further comprising:

a processor core; and

wherein the first single port SRAM array comprises a memory SRAM for the processor, and the second single port SRAM array comprises an L1 cache for the processor.

18. The integrated circuit of claim 17 , further comprising:

a third single port SRAM array comprising an L2 cache for the processor.

19. The integrated circuit of claim 18 , further comprising:

a bus interconnecting the processor, the memory SRAM, the L1 cache and the L2 cache.

20. The integrated circuit of claim 10 further comprising:

a processor core; and

wherein the first single port SRAM array comprises a memory SRAM for the processor, and the second single port SRAM array comprises an L1 cache for the processor.