Thin film transistor device and manufacturing method thereof

1. A thin film transistor device, disposed on a substrate, the thin film transistor device comprising:

a first conductivity type thin film transistor, comprising a first patterned doped layer, a first gate electrode, a first source electrode, a first drain electrode, and a first semiconductor pattern, wherein the first source electrode and the first drain electrode are electrically connected to the first patterned doped layer; and

a second conductivity type thin film transistor, comprising a second patterned doped layer, a second gate electrode, a second source electrode, a second drain electrode, and a second semiconductor pattern, wherein the second source electrode and the second drain electrode are electrically connected to the second patterned doped layer;

wherein the first semiconductor pattern and the second semiconductor pattern form a patterned semiconductor layer, the first patterned doped layer is disposed under the first semiconductor pattern, and the second patterned doped layer is disposed on the second semiconductor pattern.

2. The thin film transistor device of claim 1 , wherein the first patterned doped layer includes at least one N type dopant, and the second patterned doped layer includes at least one P type dopant.

3. The thin film transistor device of claim 1 , wherein the patterned semiconductor layer includes a polysilicon layer.

4. The thin film transistor device of claim 1 , further comprising a gate insulating layer, disposed on the patterned semiconductor layer, on the first patterned doped layer and on the second patterned doped layer, wherein the first gate electrode and the second gate electrode are disposed on the gate insulating layer.

5. The thin film transistor device of claim 4 , further comprising an inter layer dielectric, disposed on the gate insulating layer, on the first gate electrode, and on the second gate electrode, wherein the second source electrode and the second drain electrode penetrate the inter layer dielectric and the gate insulating layer for being electrically connected to the second patterned doped layer, and the first source electrode and the first drain electrode penetrate the inter layer dielectric, the gate insulating layer, and the first semiconductor pattern for being electrically connected to the first patterned doped layer.

6. The thin film transistor device of claim 4 , further comprising an inter layer dielectric, disposed on the gate insulating layer, on the first gate electrode and on the second gate electrode, wherein the second source electrode and the second drain electrode penetrate the inter layer dielectric and the gate insulating layer for being electrically connected to the second patterned doped layer, and the first source electrode and the first drain electrode are at least partially disposed between the substrate and the first patterned doped layer.

7. The thin film transistor device of claim 1 , wherein the first conductivity type thin film transistor further comprises a first gate insulating layer disposed between the substrate and the first patterned doped layer, and the first gate electrode is disposed between the first gate insulating layer and the substrate; and

the second conductivity type thin film transistor further comprises a second gate insulating layer disposed on the patterned semiconductor layer, on the first patterned doped layer, and on the second patterned doped layer, and the second gate electrode is disposed on the second gate insulating layer.

8. The thin film transistor device of claim 1 , wherein the first drain electrode is electrically connected to the second gate electrode.

9. The thin film transistor device of claim 1 , wherein the first drain electrode is electrically connected to the second source electrode, and the first gate electrode is electrically connected to the second gate electrode.

10. A manufacturing method of a thin film transistor device, comprising:

providing a substrate, wherein the substrate has a first conductivity type region and a second conductivity type region;

forming a first patterned doped layer on the first conductivity type region of the substrate;

forming a semiconductor layer on the first conductivity type region and the second conductivity type region of the substrate, wherein the semiconductor layer within the first conductivity type region covers the first patterned doped layer, and the first patterned doped layer is formed before forming the semiconductor layer;

forming a second patterned doped layer on the semiconductor layer within the second conductivity type region;

patterning the semiconductor layer, for separating the semiconductor layer within the first conductivity type region from the semiconductor layer within the second conductivity type region; and

performing at least a laser treatment on the semiconductor layer, the first patterned doped layer, and the second patterned doped layer.

11. The manufacturing method of the thin film transistor device of claim 10 , further comprising performing the laser treatment twice, respectively before and after forming the second patterned doped layer.

12. The manufacturing method of the thin film transistor device of claim 10 , wherein the laser treatment is performed after forming the second patterned doped layer.

13. The manufacturing method of the thin film transistor device of claim 10 , wherein the first patterned doped layer and the second patterned doped layer are respectively formed by a chemical vapor deposition process.

14. The manufacturing method of the thin film transistor device of claim 10 , wherein the first patterned doped layer includes at least one N type dopant, and the second patterned doped layer includes at least one P type dopant.

15. The manufacturing method of the thin film transistor device of claim 10 , wherein the semiconductor layer is transformed from an amorphous silicon layer into a polysilicon layer by the laser treatment.

16. The manufacturing method of the thin film transistor device of claim 10 , further comprising:

forming a gate insulating layer for covering the semiconductor layer within the first conductivity type region, the semiconductor layer within the second conductivity type region, and the second patterned doped layer;

forming a first gate electrode on the gate insulating layer within the first conductivity type region and a second gate electrode on the gate insulating layer within the second conductivity type region;

forming a first source electrode and a first drain electrode on the first conductivity type region, and electrically connecting the first source electrode and the first drain electrode to the first patterned doped layer; and

forming a second source electrode and a second drain electrode on the second conductivity type region, and electrically connecting the second source electrode and the second drain electrode to the second patterned doped layer.

17. The manufacturing method of the thin film transistor device of claim 16 , further comprising:

forming an inter layer dielectric on the gate insulating layer, the first gate electrode, and the second gate electrode; and

forming a plurality of contact holes in the inter layer dielectric and the gate insulating layer for partially exposing the second patterned doped layer, wherein the second source electrode and the second drain electrode are electrically connected to the second patterned doped layer via the contact holes.

18. The manufacturing method of the thin film transistor device of claim 10 , further comprising:

forming a first gate electrode on the first conductivity type region of the substrate before forming the first patterned doped layer;

forming a first gate insulating layer on the substrate for covering the first gate before forming the first patterned doped layer;

forming a second gate insulating layer on the substrate for covering the second patterned doped layer and the semiconductor layer within the second conductivity region;

forming a second gate electrode on the second gate insulating layer within the second conductivity type region;

forming a first source electrode and a first drain electrode on the first conductivity type region, and electrically connecting the first source electrode and the first drain electrode to the first patterned doped layer; and

forming a second source electrode and a second drain electrode on the second conductivity type region, and electrically connecting the second source electrode and the second drain electrode to the second patterned doped layer.

19. The manufacturing method of the thin film transistor device of claim 18 , further comprising:

forming an inter layer dielectric on the second gate insulating layer and the second gate electrode; and

forming a plurality of contact holes in the inter layer dielectric and the second gate insulating layer for partially exposing the second patterned doped layer, wherein the second source electrode and the second drain electrode are electrically connected to the second patterned doped layer via the contact holes.

20. The manufacturing method of the thin film transistor device of claim 10 , wherein the first patterned doped layer and the second patterned doped layer are formed by a non-implant process.

21. A thin film transistor device, disposed on a substrate, the thin film transistor device comprising:

a first conductivity type thin film transistor, comprising a first patterned doped layer, a first gate electrode, a first source electrode, a first drain electrode, and a first semiconductor pattern, wherein the first source electrode and the first drain electrode are electrically connected to the first patterned doped layer; and

a second conductivity type thin film transistor, comprising a second patterned doped layer, a second gate electrode, a second source electrode, a second drain electrode, and a second semiconductor pattern, wherein the second source electrode and the second drain electrode are electrically connected to the second patterned doped layer,

wherein the first semiconductor pattern and the second semiconductor pattern form a patterned semiconductor layer, the first patterned doped layer is disposed under and electrically contacts the first semiconductor pattern, and the second patterned doped layer is disposed on and electrically contacts the second semiconductor pattern.

22. The thin film transistor device of claim 21 , wherein the first patterned doped layer includes at least one N type dopant, and the second patterned doped layer includes at least one P type dopant.

23. The thin film transistor device of claim 21 , wherein the patterned semiconductor layer includes a polysilicon layer.

24. The thin film transistor device of claim 21 , further comprising a gate insulating layer, disposed on the patterned semiconductor layer, on the first patterned doped layer and on the second patterned doped layer, wherein the first gate electrode and the second gate electrode are disposed on the gate insulating layer.

25. The thin film transistor device of claim 24 , further comprising an inter layer dielectric, disposed on the gate insulating layer, on the first gate electrode, and on the second gate electrode, wherein the second source electrode and the second drain electrode penetrate the inter layer dielectric and the gate insulating layer for being electrically connected to the second patterned doped layer, and the first source electrode and the first drain electrode penetrate the inter layer dielectric, the gate insulating layer, and the first semiconductor pattern for being electrically connected to the first patterned doped layer.

26. The thin film transistor device of claim 24 , further comprising an inter layer dielectric, disposed on the gate insulating layer, on the first gate electrode and on the second gate electrode, wherein the second source electrode and the second drain electrode penetrate the inter layer dielectric and the gate insulating layer for being electrically connected to the second patterned doped layer, and the first source electrode and the first drain electrode are at least partially disposed between the substrate and the first patterned doped layer.

27. The thin film transistor device of claim 21 , wherein the first conductivity type thin film transistor further comprises a first gate insulating layer disposed between the substrate and the first patterned doped layer, and the first gate electrode is disposed between the first gate insulating layer and the substrate; and

the second conductivity type thin film transistor further comprises a second gate insulating layer disposed on the patterned semiconductor layer, on the first patterned doped layer, and on the second patterned doped layer, and the second gate electrode is disposed on the second gate insulating layer.

28. The thin film transistor device of claim 21 , wherein the first drain electrode is electrically connected to the second gate electrode.

29. The thin film transistor device of claim 21 , wherein the first drain electrode is electrically connected to the second source electrode, and the first gate electrode is electrically connected to the second gate electrode.

30. A thin film transistor device, disposed on a substrate, the thin film transistor device comprising:

a first conductivity type thin film transistor, comprising a first patterned doped layer, a first gate electrode, a first source electrode, a first drain electrode, and a first semiconductor pattern, wherein the first source electrode and the first drain electrode are electrically connected to the first patterned doped layer and the first semiconductor pattern; and

a second conductivity type thin film transistor, comprising a second patterned doped layer, a second gate electrode, a second source electrode, a second drain electrode, and a second semiconductor pattern, wherein the second source electrode and the second drain electrode are electrically connected to the second patterned doped layer and the second semiconductor pattern;

wherein the first semiconductor pattern and the second semiconductor pattern form a patterned semiconductor layer, the first patterned doped layer is disposed under the first semiconductor pattern, and the second patterned doped layer is disposed on the second semiconductor pattern.

31. The thin film transistor device of claim 30 , wherein the first patterned doped layer includes at least one N type dopant, and the second patterned doped layer includes at least one P type dopant.

32. The thin film transistor device of claim 30 , wherein the patterned semiconductor layer includes a polysilicon layer.

33. The thin film transistor device of claim 30 , further comprising a gate insulating layer, disposed on the patterned semiconductor layer, on the first patterned doped layer and on the second patterned doped layer, wherein the first gate electrode and the second gate electrode are disposed on the gate insulating layer.

34. The thin film transistor device of claim 33 , further comprising an inter layer dielectric, disposed on the gate insulating layer, on the first gate electrode, and on the second gate electrode, wherein the second source electrode and the second drain electrode penetrate the inter layer dielectric and the gate insulating layer for being electrically connected to the second patterned doped layer, and the first source electrode and the first drain electrode penetrate the inter layer dielectric, the gate insulating layer, and the first semiconductor pattern for being electrically connected to the first patterned doped layer.

35. The thin film transistor device of claim 33 , further comprising an inter layer dielectric, disposed on the gate insulating layer, on the first gate electrode and on the second gate electrode, wherein the second source electrode and the second drain electrode penetrate the inter layer dielectric and the gate insulating layer for being electrically connected to the second patterned doped layer, and the first source electrode and the first drain electrode are at least partially disposed between the substrate and the first patterned doped layer.

36. The thin film transistor device of claim 30 , wherein the first conductivity type thin film transistor further comprises a first gate insulating layer disposed between the substrate and the first patterned doped layer, and the first gate electrode is disposed between the first gate insulating layer and the substrate; and

the second conductivity type thin film transistor further comprises a second gate insulating layer disposed on the patterned semiconductor layer, on the first patterned doped layer, and on the second patterned doped layer, and the second gate electrode is disposed on the second gate insulating layer.

37. The thin film transistor device of claim 30 , wherein the first drain electrode is electrically connected to the second gate electrode.

38. The thin film transistor device of claim 30 , wherein the first drain electrode is electrically connected to the second source electrode, and the first gate electrode is electrically connected to the second gate electrode.