Methods for managing alignment and latency in interference suppression
An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data. Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.
1. An interference cancelling receiver, comprising:
at least one symbol estimator configured to operate on a signal stream to produce one or more symbol estimates from the signal stream;
one or more interference estimators coupled to the at least one symbol estimator to produce one or more of interference estimates;
one or more storage structures configured to store the one or more interference estimates at one or more locations in the one or more storage structures that are offset from a reference address by a number of addresses representative of a temporal offset between a time reference associated with the reference address and the corresponding interference estimate; and
an interference estimate combiner configured to combine one or more interference estimates aligned to the time reference to produce a composite interference estimate.
2. The interference cancelling receiver in claim 1 , wherein the at least one symbol estimator is configured to operate on Rake combined data.
3. The interference cancelling receiver in claim 1 , wherein the at least one symbol estimator is configured to operate on Equalizer combined data.
4. The interference cancelling receiver in claim 1 , wherein the signal stream comprises data selected from one of an original received signal, an interference cancelled signal, and a combination of an original received signal and an interference cancelled signal.
5. The interference cancelling receiver in claim 1 , further comprising a front-end configured to sample a received signal at a rate higher than a chipping rate and accompany sampled data at chips with chip enable indicators.
6. The interference cancelling receiver in claim 1 , further comprising:
a sampling clock domain comprising a data sampling clock;
a processing clock domain comprising a processing clock having a greater frequency than the data sampling clock and not frequency or phase locked with the data sampling clock; and
an input first-in-first-out (FIFO) buffer and an output FIFO that interconnect the sampling clock domain with the processing clock domain, wherein both the input FIFO and the output FIFO are port asynchronous.
7. The interference cancelling receiver in claim 1 , further comprising:
a sampling clock domain comprising a data sampling clock;
a processing clock domain comprising a processing clock having a greater frequency than the data sampling clock and not frequency or phase locked with the data sampling clock; and
an input first-in-first-out (FIFO) buffer and an output FIFO that interconnect the sampling clock domain with the processing clock domain, wherein both the input FIFO and the output FIFO are port synchronous and include a retiming circuit configured to address frequency and phase differences between the data sampling clock and the processing clock.
8. A method for performing interference cancellation comprising:
computing symbol estimates from a combined data stream;
processing the symbol estimates to produce modified symbol estimates;
using said modified symbol estimates to create a plurality of interference estimates;
aligning at least one of the plurality of interference estimates with respect to a time reference by storing the plurality of interface estimates at a plurality of locations in one or more storage structures that are offset from a reference address by a number of addresses representative of a temporal offset between the time reference and the corresponding interference estimate;
combining the plurality of interference estimates aligned to the time reference to create a combined interference estimate; and
using the combined interference estimate to create at least one interference cancelled signal stream.
9. The method recited in claim 8 , wherein said aligning comprises aligning chip-level data from a plurality of paths from a single source to a symbol boundary of each of said plurality of paths to produce a plurality of aligned paths.
10. The method recited in claim 8 , wherein said combining comprises summing the plurality of interference estimates.
11. The method recited in claim 8 , wherein the combined data stream comprises interference cancelled data.
12. The method recited in claim 8 , wherein the combined data stream comprises a combination of interference cancelled data and raw signal.
13. The method recited in claim 8 , further comprising:
sampling a received signal at a rate higher than a chipping rate; and
accompanying the sampled data at chips with chip enable indicators.
14. The method recited in claim 8 , further comprising:
operating a sampling clock domain based on a data sampling clock;
operating a processing clock domain based on a processing clock having a greater frequency than the data sampling clock and not frequency or phase locked with the data sampling clock; and
interconnecting the sampling clock domain and the processing clock domain with an input first-in-first-out (FIFO) buffer and an output FIFO that both are port asynchronous.
15. The method recited in claim 8 , further comprising:
operating a sampling clock domain based on a data sampling clock;
operating a processing clock domain based on a processing clock having a greater frequency than the data sampling clock domain and not frequency or phase locked with the data sampling clock; and
interconnecting the sampling clock domain and the processing clock domain with an input first-in-first-out (FIFO) buffer and an output FIFO that are both port synchronous and that both include a retiming circuit configured to address frequency and phase differences between the data sampling clock and the processing clock.