SEMICONDUCTOR DEVICE HAVING DATA OUTPUT BUFFERS
A semiconductor device includes: a plurality of power supply pads to which external voltages are supplied; a plurality of data output pads; power supply main lines that are connected to the respective corresponding power supply pads in common; a plurality of power supply branch lines that are branched from the power supply main lines, respectively; a plurality of output buffers that operate with power supply voltages supplied from the respective corresponding power supply branch lines, and drive respective corresponding data output pads; and low-pass filter circuits that are provided on the respective power supply branch lines.
1 . A semiconductor device comprising:
a plurality of first power supply pads supplied with a first external voltage;
a plurality of data output pads;
a first power supply line connected in common to the first power supply pads;
a plurality of output buffers connected to the first power supply line in common, each of the output buffers being connected to a corresponding one of the data output pads; and
a plurality of low-pass filter circuits each interposed between the first power supply line and a corresponding one of the output buffers.
2 . The semiconductor device as claimed in claim 1 , further comprising:
a plurality of second power supply pads supplied with a second external voltage; and
a second power supply line connected in common to the second power supply pads,
wherein each of the low-pass filter circuits includes a first resistive element connected between the first power supply line and the corresponding one of the output buffers, and a first capacitive element having one electrode connected to one end of the first resistive element and other electrode connected to the second power supply line.
3 . The semiconductor device as claimed in claim 2 , wherein each of the low-pass filter circuits further includes a second resistive element connected between the second power supply line and the corresponding one of the output buffers, and a second capacitive element having one electrode connected to one end of the second resistive element and other electrode connected to the first power supply line.
4 . The semiconductor device as claimed in claim 2 , wherein the first resistive element in each of the low-pass filter circuits includes a first transistor.
5 . The semiconductor device as claimed in claim 4 , further comprising a control circuit supplying a control signal to a control electrode of the first transistor in each of the low-pass filter circuits, the control circuit bringing the first transistor in each of the low-pass filter circuits into an nonconductive state in a first period after starting to supply the first and second external voltages.
6 . The semiconductor device as claimed in claim 5 , further comprising a first internal voltage generation circuit generating a first internal voltage based on the first external voltage,
wherein the control circuit supplies the first internal voltage to the control electrode of the first transistor in each of the low-pass filter circuits to bring the first transistor in each of the low-pass filter circuits into a conductive state in a second period subsequent to the first period.
7 . The semiconductor device as claimed in claim 5 , further comprising:
a second internal voltage generation circuit generating a second internal voltage based on the first external voltage; and
an internal circuit supplying an input signal to the output buffers,
wherein the internal circuit operates on the second internal voltage.
8 . The semiconductor device as claimed in claim 7 , further comprising a second transistor interposed between the first power supply pads and the second internal voltage generation circuit,
wherein the control circuit supplies the control signal to a control electrode of the second transistor.
9 . The semiconductor device as claimed in claim 7 , wherein the first internal voltage is higher than the first external voltage, and the second internal voltage is lower than the first external voltage.
10 . The semiconductor device as claimed in claim 1 , further comprising:
a pair of data strobe pads; and
a pair of strobe buffers connected to the first power supply line in common, each of the pair of strobe buffers driving a corresponding one of the pair of data strobe pads at substantially a same timing as that at which each of the output buffers drives the corresponding one of the data output pads.
11 . A semiconductor device comprising:
a plurality of first power supply pads supplied with a first external voltage;
a plurality of data output pads;
a first power supply line connected in common to the first power supply pads;
a plurality of output buffers operating on the first external voltage supplied from the first power supply line, each of the output buffers driving a corresponding one of the data output pads to either one of first and second logic levels when activated; and
a plurality of low-pass filter circuits each provided for a corresponding one of the output buffers and attenuating a noise caused by an operation of the corresponding one of the output buffers before the noise reaches to the first power supply line.
12 . The semiconductor device as claimed in claim 11 , further comprising:
a plurality of second power supply pads supplied with a second external voltage; and
a second power supply line connected in common to the second power supply pads,
wherein each of the low-pass filter circuits includes a first resistive element connected between the first power supply line and the corresponding one of the output buffers, and a first capacitive element having one electrode connected to one end of the first resistive element and other electrode connected to the second power supply line.
13 . The semiconductor device as claimed in claim 12 , wherein each of the low-pass filter circuits further includes a second resistive element connected between the second power supply line and the corresponding one of the output buffers, and a second capacitive element having one electrode connected to one end of the second resistive element and other electrode connected to the first power supply line.
14 . The semiconductor device as claimed in claim 12 , wherein the first resistive element in each of the low-pass filter circuits includes a first transistor.
15 . The semiconductor device as claimed in claim 14 , further comprising a control circuit supplying a control signal to a control electrode of the first transistor in each of the low-pass filter circuits, the control circuit bringing the first transistor in each of the low-pass filter circuits into an nonconductive state in a first period after starting to supply the first and second external voltages.
16 . The semiconductor device as claimed in claim 15 , further comprising a first internal voltage generation circuit generating a first internal voltage based on the first external voltage,
wherein the control circuit supplies the first internal voltage to the control electrode of the first transistor in each of the low-pass filter circuits to bring the first transistor in each of the low-pass filter circuits into a conductive state in a second period subsequent to the first period.
17 . The semiconductor device as claimed in claim 15 , further comprising:
a second internal voltage generation circuit generating a second internal voltage based on the first external voltage; and
an internal circuit supplying an input signal to the output buffers,
wherein the internal circuit operates on the second internal voltage.
18 . The semiconductor device as claimed in claim 17 , further comprising a second transistor interposed between the first power supply pads and the second internal voltage generation circuit,
wherein the control circuit supplies the control signal to a control electrode of the second transistor.
19 . The semiconductor device as claimed in claim 17 , wherein the first internal voltage is higher than the first external voltage, and the second internal voltage is lower than the first external voltage.
20 . The semiconductor device as claimed in claim 11 , wherein
the data output pads include a plurality of data strobe pads, and
the output buffers include a plurality of strobe buffers, each of the strobe buffers driving a corresponding one of the data strobe pads to either one of the first and second logic levels.