Reference voltage circuit and semiconductor integrated circuit

1. A reference voltage circuit comprising:

a first amplifier including first and second input terminals, coupled to a first power source line and a second power source line, configured to output a reference voltage;

a first load device and a first PN junction device coupled in series between a reference voltage line to which the reference voltage is applied and the second power source line;

second and third load devices and a second PN junction device coupled in series between the reference voltage line and the second power source line, the first input terminal being coupled to a first coupling node which connects the first load device and the first PN junction device, the second input terminal being coupled to a second coupling node which connects the second load device and the third load device;

an offset voltage reduction circuit configured to reduce an offset voltage between the first and second input terminals at the first amplifier;

a coupling node potential takeout circuit configured to take out potentials of the first and second coupling nodes; and

an area adjustment circuit configured to adjust an area of the second PN junction device in accordance with the potentials of the first and second coupling nodes which are taken out by the coupling node potential takeout circuit.

2. The reference voltage circuit as claimed in claim 1 , wherein the reference voltage circuit further comprises:

a first switch coupled to the first coupling node and the coupling node potential takeout circuit; and

a second switch coupled to the second coupling node and the coupling node potential takeout circuit, wherein

the first and second switches are controlled to take out the potentials of the first and second connection nods as outputs of the coupling node potential takeout circuit.

3. The reference voltage circuit as claimed in claim 2 , wherein

the coupling node potential takeout circuit takes out the potentials of the first and second coupling nodes through a regulator circuit which outputs an internal voltage.

4. The reference voltage circuit as claimed in claim 3 , wherein

the reference voltage circuit further comprises a third switch coupled to the output of the first amplifier and the regulator circuit;

the regulator circuit includes a first circuit configured to output the internal voltage, a second circuit configured to take out the potentials of the first and second coupling nodes as output voltages of the regulator circuit, and a fourth switch configured to switch operations of the first and second circuits;

the regulator circuit turns off the first, second, and fourth switches and turns on the third switch when generating the internal voltage;

the regulator circuit turns on the first and fourth switches and turns off the second and third switches when taking out the potential of the first coupling node as an output voltage of the regulator circuit; and

the regulator circuit turns on the second and fourth switches and turns off the first and third switches when taking out the potential of the second coupling node as the output voltage of the regulator circuit.

5. The reference voltage circuit as claimed in claim 2 , wherein

the coupling node potential takeout circuit is a buffer amplifier and takes out the potentials of the first and second coupling nodes as an output voltage of the buffer amplifier.

6. The reference voltage circuit as claimed in claim 5 , wherein

the buffer amplifier turns on the first switch and turns off the second switch when taking out the potential of the first coupling node as the output voltage of the buffer amplifier; and

the buffer amplifier turns off the first switch and turns on the second switch when taking out the potential of the second coupling node as the output voltage of the buffer amplifier.

7. The reference voltage circuit as claimed in claim 1 , wherein the reference voltage circuit further comprises:

a resistance ratio control circuit configured to control a ratio of the resistance values of the second load device and the third load device in accordance with the potentials of the first and second coupling nodes which are taken out from the coupling node potential takeout circuit.

8. The reference voltage circuit as claimed in claim 7 , wherein

the offset voltage reduction circuit is built in the first amplifier and reduces the offset voltage between the first and second input terminals by an offset adjustment signal.

9. The reference voltage circuit as claimed in claim 7 , wherein the offset voltage reduction circuit comprises:

a second amplifier coupled to the first amplifier, including third and fourth input terminals, and coupled to the first power source line and the second power source line; and

an offset adjustment voltage generation circuit configured to generate a voltage which is input to the third and fourth input terminals of the second amplifier and configured to reduce the offset voltage between the first and second input terminals of the first amplifier through the second amplifier.

10. The reference voltage circuit as claimed in claim 9 , wherein

the second amplifier includes a single-stage third amplification circuit; and

a current output of the third amplification circuit is added to two current outputs of an input differential circuit of the first amplification circuit.

11. The reference voltage circuit as claimed in claim 9 , wherein

the offset adjustment voltage generation circuit generates a voltage which is input to the first and fourth input terminals so as to cancel the offset voltage between the first and second input terminals.

12. The reference voltage circuit as claimed in claim 1 , wherein

the first amplifier comprises as a two-stage configuration first amplification circuit and second amplification circuit; and

the first amplification circuit includes an input differential circuit and a fourth load device which converts two current outputs of the input differential circuit to a voltage value.

13. The reference voltage circuit as claimed in claim 12 , wherein

the first PN junction device is a first PNP transistor, the second PN junction device is a second PNP transistor, the first load device is a first resistor, the second load device is a second resistor, the third load device is a third resistor, and the fourth load device is a load transistor; and

the first PNP transistor and the second PNP transistor are biased to different current densities.

14. A semiconductor integrated circuit comprising:

a reference voltage circuit;

a low voltage detection circuit which monitors a power source voltage of a first power source line;

an internal circuit; and

a regulator circuit which generates an internal voltage for operating the internal circuit from a first power source voltage of the first power source line which is supplied from the outside, wherein the reference voltage circuit comprises:

a first amplifier including first and second input terminals, coupled to a first power source line and a second power source line, configured to output a reference voltage;

a first load device and a first PN junction device coupled in series between a reference voltage line to which the reference voltage is applied and the second power source line;

second and third load devices and a second PN junction device coupled in series between the reference voltage line and the second power source line, the first input terminal being coupled to a first coupling node which connects the first load device and the first PN junction device, the second input terminal being coupled to a second coupling node which connects the second load device and the third load device;

an offset voltage reduction circuit configured to reduce an offset voltage between the first and second input terminals at the first amplifier;

a coupling node potential takeout circuit configured to take out potentials of the first and second coupling nodes; and

an area adjustment circuit configured to adjust an area of the second PN junction device in accordance with the potentials of the first and second coupling nodes which are taken out by the coupling node potential takeout circuit.

15. The semiconductor integrated circuit as claimed in claim 14 , wherein

the coupling node potential takeout circuit takes out the potentials of the first and second coupling nodes through a regulator circuit which outputs an internal voltage.