High data rate transmitter and receiver
View Patent ↗A high-speed transmitter and receiver are provided. In one embodiment, a transmitter comprises a baseband processor structured to receive data and to convert the data into a multiplicity of high and low signal values, with each high and low signal value having a first timing interval. A local oscillator generates a clock signal at a second timing interval and a digital circuit combines the high and low signal values with the clock signal to produce a transmission signal directly at a transmission frequency. A receiver is configured to receive the signal. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
1. A transmitter comprising:
a baseband processor configured to:
receive first data;
prepend second data to the first data to generate combined data; and
convert the combined data into a multiplicity of high and low signal values, wherein each high and low signal value has a first timing interval;
a local oscillator configured to generate a clock signal at a second timing interval; and
a digital circuit configured to combine the high and low signal values with the clock signal to produce a transmission signal directly at a transmission frequency.
2. The transmitter of claim 1 , further comprising a data interface configured to pass the data to the baseband processor, wherein the data interface is selected from a group consisting of: Universal Serial Bus standard, an IEEE 1394 standard, a Peripheral Component Interconnect standard, a Peripheral Component Interconnect Express standard, a MILSPEC-1760 standard, an Ethernet standard, and a MILSPEC-1553 standard.
3. The transmitter of claim 1 , wherein the digital circuit comprises an adjustable chipping code to spread the transmission signal.
4. The transmitter of claim 3 , wherein the chipping code is selected from a group consisting of: a 256-bit code, a 64-bit code, a 32-bit code, a 16-bit code, an 8-bit code, a 4-bit code, a 2-bit code, and a 1-bit code.
5. The transmitter of claim 3 , wherein the adjustable chipping code is adjusted in response to a communication channel condition, wherein the communication channel condition is selected from: a bit-error-rate, a received signal strength indicator, and a packet error rate.
6. The transmitter of claim 1 , wherein the baseband processor is structured to determine a data encoding rate, the data encoding rate selected from a group consisting of: full rate encoding, 1/8th rate encoding, 1/4 rate encoding, 3/8th rate encoding 1/2 rate encoding, 5/8th rate encoding, 7/8th rate encoding, and 3/4 rate encoding.
7. The transmitter of claim 1 , wherein the first timing interval is between 133 picoseconds and 2 nanoseconds.
8. The transmitter of claim 1 , wherein the second timing interval is between 100 picoseconds and 333 picoseconds.
9. The transmitter of claim 1 , wherein the second timing interval is an integer multiple of the first timing interval.
10. The transmitter of claim 1 , wherein a ratio of the second timing interval to the first timing interval is between 20 percent and 200 percent.
11. The transmitter of claim 1 , wherein the digital circuit is selected from a group consisting of: an “exclusive or” gate, an “and” gate, and a multiplexer.
12. The transmitter of claim 1 , wherein the transmission frequency is between 3.0 Giga-Hertz and 11.0 Giga-Hertz.
13. The transmitter of claim 1 , wherein the transmission signal is transmitted through a wire media to a receiver, wherein the wire media is selected from a group consisting of: a an optical fiber ribbon, a fiber optic cable, a single mode fiber optic cable, a multi-mode fiber optic cable, a twisted pair wire, an unshielded twisted pair wire, a plenum wire, a PVC wire, and a coaxial cable.
14. A method of transmitting data, the method comprising:
providing first data;
prepending second data to the first data to generate combined data
converting, using a processor, the combined data into a multiplicity of high and low signal values, wherein each high and low signal value has a first timing interval;
generating a clock signal at a second timing interval; and
combining the high and low signal values with the clock signal to produce a transmission signal directly at a transmission frequency.
15. The method of claim 14 , further comprising adjusting a chipping code to spread the transmission signal.
16. The method of claim 15 , wherein the chipping code is selected from a group consisting of: a 256-bit code, a 64-bit code, a 32-bit code, a 16-bit code, an 8-bit code, a 4-bit code, a 2-bit code, and a 1-bit code.
17. The method of claim 15 , wherein adjusting the chipping code is performed in response to a communication channel condition, the communication channel condition selected from: a bit-error-rate, a received signal strength indicator, and a packet error rate.
18. The method of claim 14 , further comprising determining a data encoding rate, wherein the data encoding rate is selected from a group consisting of: full rate encoding, 1/2 rate encoding, and 3/4 rate encoding.
19. The method of claim 14 , wherein the first timing interval is between 133 picoseconds and 2 nanoseconds.
20. The method of claim 14 , wherein the second timing interval is between 100 picoseconds and 333 picoseconds.
21. The method of claim 14 , wherein the second timing interval is an integer multiple of the first timing interval.
22. The method of claim 14 , wherein a ratio of the second timing interval to the first timing interval is between 20 percent and 200 percent.
23. The method of claim 14 , wherein the transmission frequency is between 3.0 Giga-Hertz and 11.0 Giga-Hertz.