IP Library Granted Patent US 8,476,628
Granted Patent B2
US 8,476,628 · App. 13/317,373 · Granted Jul 2, 2013

Device using oxide semiconductor, display device, and electronic apparatus

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Quick Facts
Patent No.
US 8,476,628
App. No.
13/317,373
Granted
Jul 2, 2013
Kind
B2
Abstract

Disclosed herein is a device using an oxide semiconductor, the device including a circuit part configured to include a thin film transistor using the oxide semiconductor as a channel material, wherein the circuit part has a lower interconnect, an upper interconnect, and an interlayer insulating film, the interlayer insulating film includes an oxide semiconductor layer and a channel protective layer, and the channel protective layer is interposed between an outer circumferential surface of a rising part of the oxide semiconductor layer corresponding to thickness of the lower interconnect and the upper interconnect.

Claims (41)

1. A device using an oxide semiconductor, the device comprising:

a circuit part configured to include a thin film transistor using the oxide semiconductor as a channel material and at least one wiring intersection portion,

wherein the wiring intersection portion has an interlayer insulating film between a lower interconnect and an upper interconnect, the upper interconnect intersecting the lower interconnect,

wherein the interlayer insulating film includes an oxide semiconductor layer and a channel protective layer, the oxide semiconductor layer and the channel protective layer being stacked over the lower interconnect with intermediary of a gate insulating film, and

wherein the channel protective layer is interposed between an outer circumferential surface of a rising part of the oxide semiconductor layer corresponding to thickness of the lower interconnect and the upper interconnect.

2. The device using an oxide semiconductor according to claim 1 , wherein a peripheral end of the oxide semiconductor layer is electrically short-circuited with the upper interconnect.

3. The device using an oxide semiconductor according to claim 2 , wherein the peripheral end of the oxide semiconductor layer exists at the same outer circumferential position as an outer circumferential position of a peripheral end of the channel protective layer.

4. The device using an oxide semiconductor according to claim 1 , wherein a peripheral end of the oxide semiconductor layer is electrically insulated from the upper interconnect.

5. A device using an oxide semiconductor, the device comprising:

a circuit part configured to include a thin film transistor using the oxide semiconductor as a channel material,

wherein the circuit part has an interlayer insulating film between a lower interconnect and an upper interconnect, the upper interconnect intersecting the lower interconnect, and

wherein the interlayer insulating film is over the lower interconnect with intermediary of a gate insulating film.

6. A device using an oxide semiconductor, the device comprising:

a circuit part configured to include a thin film transistor and at least one wiring intersection portion,

wherein the wiring intersection portion has an interlayer insulating film between a lower interconnect and an upper interconnect, the upper interconnect intersecting the lower interconnect, and

wherein the interlayer insulating film includes an oxide semiconductor layer and a protective layer, the oxide semiconductor layer and the protective layer being stacked over the lower interconnect with intermediary of a gate insulating film, and

wherein the protective layer is interposed between an outer circumferential surface of a rising part of the oxide semiconductor layer and the upper interconnect.

7. A display device comprising:

a pixel array part configured to be formed by arranging pixels each including an electrooptical element; and

a circuit part configured to include a thin film transistor using an oxide semiconductor as a channel material and at least one wiring portion,

wherein the wiring portion has an interlayer insulating film between a lower interconnect and a upper interconnect, the upper interconnect intersecting the lower interconnect, and

wherein the interlayer insulating film includes an oxide semiconductor layer and a channel protective layer, the oxide semiconductor layer and the channel protective layer being stacked over the lower interconnect with intermediary of a gate insulating film, and

wherein the channel protective layer is interposed between an outer circumferential surface of a rising part of the oxide semiconductor layer corresponding to thickness of the lower interconnect and the upper interconnect.

8. The display device according to claim 7 , wherein the circuit part is mounted on the same substrate as a substrate of the pixel array part.

9. A display device comprising:

a pixel array part configured to be formed by arranging pixels each including an electrooptical element; and

a circuit part configured to include a thin film transistor using an oxide semiconductor as a channel material,

wherein the circuit part has an interlayer insulating film between a lower interconnect and an upper interconnect, the upper interconnect intersecting the lower interconnect, and

wherein the interlayer insulating film over the lower interconnect with intermediary of a gate insulating film.

10. The display device according to claim 9 , wherein the circuit part is mounted on the same substrate as a substrate of the pixel array part.

11. Electronic apparatus having a display device comprising:

a pixel array part configured to be formed by arranging pixels each including an electrooptical element; and

a circuit part configured to include a thin film transistor using an oxide semiconductor as a channel material and at least one wiring intersection portion,

wherein the wiring intersection portion has an interlayer insulating film between a lower interconnect and an upper interconnect, the upper interconnect intersecting the lower interconnect, and

wherein the interlayer insulating film includes an oxide semiconductor layer and a channel protective layer, the oxide semiconductor layer and the channel protective layer being stacked over the lower interconnect with intermediary of a gate insulating film, and

wherein the channel protective layer is interposed between an outer circumferential surface of a rising part of the oxide semiconductor layer corresponding to thickness of the lower interconnect and the upper interconnect.

12. Electronic apparatus having a display device comprising:

a pixel array part configured to be formed by arranging pixels each including an electrooptical element; and

a circuit part configured to include a thin film transistor using an oxide semiconductor as a channel material,

wherein the circuit part has an interlayer insulating film between a lower interconnect and an upper interconnect, the upper interconnect intersecting the lower interconnect, and

wherein the interlayer insulating film is over the lower interconnect with intermediary of a gate insulating film.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2015
From: SONY CORPORATION
To: JOLED INC.
Reel/Frame 036106/0355 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2011
From: MINAMI, TETSUO; UCHINO, KATSUHIDE
To: SONY CORPORATION
Reel/Frame 027238/0352 →