Multilayer wiring substrate and method of manufacturing the same

1. A multilayer wiring substrate comprising:

an interlayer insulation layer isolating a lower conductor layer from an upper conductor layer;

via holes formed in the interlayer insulation layer; and

via conductors formed in the respective via holes for connecting the lower conductor layer and the upper conductor layer;

wherein:

a surface of the interlayer insulation layer is a rough surface;

the via holes open at the rough surface of the interlayer insulation layer;

stepped portions are formed in opening verge regions of the surface around the via holes such that the stepped portions are recessed from peripheral regions of the interlayer insulation layer around the opening verge regions;

the stepped portions are higher in surface roughness than the peripheral regions;

the upper conductor layer comprises lands connected to upper ends of the corresponding via conductors continuously; and

the via conductors and the upper conductor layers cover a top surface of the stepped portion and a top surface of the peripheral region.

2. A multilayer wiring substrate according to claim 1 , wherein maximum diameters of the lands are greater than those of the corresponding stepped portions.

3. A multilayer wiring substrate according to claim 1 , wherein the via holes, the stepped portions, and the lands are disposed concentrically.

4. A multilayer wiring substrate according to claim 1 , wherein the stepped portions have a depth of 1 μm to 3 μm inclusive and a surface roughness of less than 1 μm.

5. A multilayer wiring substrate according to claim 1 , wherein the stepped portions have a width of 10 μm to 30 μm inclusive.

6. A multilayer wiring substrate according to claim 1 , wherein the interlayer insulation layer is formed of an insulation resin material containing an inorganic filler in an amount of 50% by weight or greater.

7. A multilayer wiring substrate according to claim 1 , wherein a thickness of portions of the upper conductor layer formed on the stepped portions of the interlayer insulation layer is greater than a thickness of portions of the upper conductor layer formed on the peripheral regions of the interlayer insulation layer.

8. A multilayer wiring substrate according to claim 1 , wherein the interlayer insulation layer is a single layer.

9. A multilayer wiring substrate comprising:

an interlayer insulation layer;

via conductors charged into via holes formed in the interlayer insulation layer;

terminal pads embedded in a terminal pad side of the interlayer insulation layer; and

an interlayer wiring formed on a surface of an interlayer wiring side of the interlayer insulation layer that is opposite the terminal pad side, the interlayer wiring being connected to the terminal pads via the via conductors;

wherein:

the via holes are shaped such that their diameters increase from the terminal pad side toward the interlayer wiring side;

stepped portions are formed in respective opening verge regions of the surface of the interlayer insulation layer around the via holes such that the stepped portions are recessed from peripheral regions of the surface of the interlayer insulation layer around the opening verge regions;

the stepped portions are higher in surface roughness than the peripheral regions;

the interlayer wiring includes lands connected to upper ends of the via conductors continuously; and

the lands cover a top surface of the stepped portion and a top surface of the peripheral region.

10. A multilayer wiring substrate according to claim 9 , wherein:

the interlayer wiring is formed on the stepped portions and the peripheral regions; and

other via conductors are connected to portions of the interlayer wiring formed on the peripheral regions.

11. A multilayer wiring substrate according to claim 9 , wherein a thickness of portions of the interlayer wiring formed on the stepped portions of the interlayer insulation layer is greater than a thickness of portions of the interlayer wiring formed on the peripheral regions of the interlayer insulation layer.

12. A multilayer wiring substrate according to claim 9 , wherein maximum diameters of the lands are greater than those of the corresponding stepped portions.

13. A multilayer wiring substrate according to claim 9 , wherein the terminal pads are connected to a semiconductor chip via solder bumps.

14. A multilayer wiring substrate according to claim 9 , wherein the interlayer insulation layer is a single layer.

15. A method of manufacturing a multilayer wiring substrate, comprising:

an interlayer insulation layer forming step of forming an interlayer insulation layer which covers a lower conductor layer;

a laser irradiation step of irradiating predetermined via hole formation positions of the interlayer insulation layer with a laser beam having a first laser energy to form via holes in the interlayer insulation layer, and irradiating predetermined stepped portion formation positions of the interlayer insulation layer in opening verge regions of a surface of the interlayer insulation layer around the via holes with a laser beam having a second laser energy weaker than the first laser energy such that the stepped portion are recessed from peripheral regions of the interlayer insulation layer around the opening verge regions; and

a roughening step of roughening, after the laser irradiation step, the interlayer insulation layer so as to make an entire surface of the interlayer insulation layer a rough surface and to make surfaces of the stepped portions higher in surface roughness than the peripheral regions;

a via conductor forming step of forming, after the roughening step, via conductors in the respective via holes for connecting the lower conductor layer and an upper conductor layer, the via holes opening at the rough surface of the interlayer insulation layer; and

an upper conductor layer forming step of forming, after the via conductor forming step, the upper conductor layer that includes lands connected to upper ends of the corresponding via conductors continuously, wherein

the via conductors and the upper conductor layers cover a top surface of the stepped portion and a top surface of the peripheral region.