Semiconductor device including power-on reset circuit
View Patent ↗A semiconductor device including a power-on-reset (POR) circuit. The semiconductor device includes a driving voltage generator configured to generate a first voltage that rises at a first slope and subsequently rises at a second slope greater than the first slope and a first POR signal generator configured to receive the first voltage and generate a first POR signal having a first ramp-up time.
1. A semiconductor device comprising:
a driving voltage generator configured to generate a first voltage that rises at a first slope and subsequently rises at a second slope greater than the first slope; and
a first power-on-reset (POR) signal generator configured to receive the first voltage and generate a first POR signal having a first ramp-up time, and turn off the first POR signal while the first voltage rises at the second slope.
2. The semiconductor device of claim 1 , further comprising a storage unit configured to store data and initialize the stored data by receiving the first POR signal.
3. The semiconductor device of claim 1 , wherein the first POR signal generator includes an asymmetric inverter configured to receive the first voltage, invert the first voltage, and generate an output signal that sharply decreases with a rise of the first voltage.
4. The semiconductor device of claim 1 , wherein the driving voltage generator includes a beta multiplier.
5. The semiconductor device of claim 1 , wherein the driving voltage generator is further configured to receive a supply voltage rising at a third slope and generate the first voltage,
wherein the first slope at which the first voltage rises is less than the third slope, and the second slope at which the first voltage rises is greater than the third slope.
6. A semiconductor device comprising:
a driving voltage generator configured to generate a first voltage that rises at a first slope and subsequently rises at a second slope greater than the first slope;
a first power-on-reset (POR) signal generator configured to receive the first voltage and generate a first POR signal having a first ramp-up time; and
a second POR signal generator configured to receive a second voltage and generate a second POR signal having a second ramp-up time,
wherein the first ramp-up time is longer than the second ramp-up time.
7. The semiconductor device of claim 6 , further comprising:
a voltage divider connected between a first power supply source and a second power supply source and configured to provide the second voltage from an output terminal thereof;
a capacitive unit connected between the output terminal of the voltage divider and the second power supply source; and
a storage unit configured to store data and initialize the stored data by receiving the first POR signal or the second POR signal, wherein the second POR signal generator is connected to the output terminal of the voltage divider.
8. A semiconductor device comprising:
a driving voltage generator configured to generate a first voltage that rises at a first slope and subsequently rises at a second slope greater than the first slope;
a first power-on-reset (POR) signal generator configured to receive the first voltage and generate a first POR signal having a first ramp-up time;
a reference voltage generator configured to generate a reference voltage; and
a comparator configured to generate a second POR signal having a second ramp-up time,
wherein the first ramp-up time is less than the second ramp-up time.
9. The semiconductor device of claim 8 , further comprising:
a voltage divider connected between a first power supply source and a second power supply source and configured to provide a second voltage from an output terminal thereof; and
a storage unit configured to store data and initialize the stored data by receiving the first POR signal or the second POR signal,
wherein the comparator is further configured to compare the second voltage of the output terminal of the voltage divider with the reference voltage.
10. A semiconductor device comprising:
a driving voltage generator configured to generate a first voltage that rises at a first slope and subsequently rises at a second slope greater than the first slope;
a first power-on-reset (POR) signal generator configured to receive the first voltage and generate a first POR signal having a first ramp-up time;
a second POR signal generator configured to generate a second POR signal having a second ramp-up time; and
an undervoltage-lockout (UVLO) module configured to generate a third POR signal having a third ramp-up time.
11. The semiconductor device of claim 10 , wherein the first ramp-up time is greater than the second ramp-up time and less than the third ramp-up time.
12. The semiconductor device of claim 10 , further comprising a storage unit configured to store data and initialize the stored data by receiving at least one of the first through third POR signals.
13. The semiconductor device of claim 10 , further comprising a voltage divider connected between a first power supply source and a second power supply source, wherein the second POR signal generator and the UVLO module receive a voltage from the voltage divider and generate the second and third POR signals, respectively.
14. The semiconductor device of claim 10 , wherein the UVLO module comprises:
a voltage divider connected between a first power supply source and a second power supply source and configured to provide a second voltage from an output terminal thereof;
a reference voltage generator configured to generate a reference voltage; and a comparator configured to compare the second voltage of the output terminal of the voltage divider with the reference voltage and generate the third POR signal having the third ramp-time.
15. The semiconductor device of claim 14 , further comprising a capacitive unit connected between the output terminal of the voltage divider and the second power supply source,
wherein the second POR signal generator is connected to the output terminal of the voltage divider and configured to receive the second voltage and generate the second POR signal having the second ramp-up time.
16. The semiconductor device of claim 15 , wherein the first ramp-up time is longer than the second ramp-up time and shorter than the third ramp-up time.
17. The semiconductor device of claim 10 , further comprising:
a voltage divider connected between a first power supply source and a second power supply source and configured to provide a second voltage from an output terminal thereof;
a capacitive unit connected between the output terminal of the voltage divider and the second power supply source;
a second POR signal generator connected to the output terminal of the voltage divider and configured to receive the second voltage and generate the second POR signal having the second ramp-up time;
a reference voltage generator configured to generate a reference voltage; and a comparator configured to compare the second voltage of the output terminal of the voltage divider with the reference voltage and generate the third POR signal having the third ramp-up time.
18. The semiconductor device of claim 17 , wherein the first ramp-up time is longer than the second ramp-up time and shorter than the third ramp-up time.
19. A semiconductor device comprising:
a driving voltage generator configured to generate a first voltage that rises at a first slope and subsequently rises at a second slope greater than the first slope;
a first power-on-reset (POR) signal generator configured to receive the first voltage and generate a first POR signal having a first ramp-up time;
a voltage divider connected between a first power supply source and a second power supply source and configured to provide a second voltage from an output terminal thereof;
a capacitive unit connected between the output terminal of the voltage divider and the second power supply source;
a second POR signal generator connected to the output terminal of the voltage divider and configured to receive the second voltage and generate a second POR signal having a second ramp-up time;
a reference voltage generator configured to generate a reference voltage;
a comparator configured to compare the second voltage of the output terminal of the voltage divider with the reference voltage and generate a third POR signal having a third ramp-up time; and
a storage unit configured to store data, receive at least one of the first through third POR signals, and initialize the stored data,
wherein the first ramp-up time is longer than the second ramp-up time and shorter than the third ramp-up time.
20. A semiconductor device comprising:
a voltage divider connected between a first power supply source and a second power supply source and configured to provide a first voltage through an output terminal thereof;
a capacitive unit connected between the output terminal of the voltage divider and the second power supply source;
a power-on-reset (POR) signal generator connected to the output terminal of the voltage divider and configured to receive the first voltage and generate a first POR signal having a first ramp-up time;
a reference voltage generator configured to generate a reference voltage; and
a comparator configured to compare the first voltage of the output terminal of the voltage divider with the reference voltage and generate a second POR signal having a second ramp-up time,
wherein the first ramp-up time is shorter than the second ramp-up time.