IP Library Granted Patent US 8,952,400
Granted Patent B2
US 8,952,400 · App. 13/325,225 · Granted Feb 10, 2015

Light emitting diode and light emitting device package including the same

Inventors: Myung Hoon Jung (Seoul, KR); Hyun chul Lim (Seoul, KR); Sul Hee Kim (Seoul, KR); Rak Jun Choi (Seoul, KR)
Assignee: LG Innotek Co., Ltd.
H01L33/10F21K9/13H01L33/025F21Y2101/02H01L21/0237H01L21/0243H01L21/02458H01L21/02521H01L21/0254H01L21/02639H01L21/02647H01L33/007H01L33/22H01L33/24
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,952,400
App. No.
13/325,225
Granted
Feb 10, 2015
Kind
B2
Abstract

A light emitting diode is disclosed. The disclosed light emitting diode includes a light emitting structure including a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer. The first-conductivity-type semiconductor layer, active layer, and second-conductivity-type semiconductor layer are disposed to be adjacent to one another in a same direction. The active layer includes well and barrier layers alternately stacked at least one time. The well layer has a narrower energy bandgap than the barrier layer. The light emitting diode also includes a mask layer disposed in the first-conductivity-type semiconductor layer, a first electrode disposed on the first-conductivity-type semiconductor layer, and a second electrode disposed on the second-conductivity-type semiconductor layer. The first-conductivity-type semiconductor layer is formed with at least one recess portion.

Claims (51)

1. A light emitting diode comprising:

a light emitting structure including a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer, wherein the first-conductivity-type semiconductor layer, the active layer, and the second-conductivity-type semiconductor layer are disposed to be adjacent to one another in a same direction, the active layer includes well and barrier layers alternately stacked at least one time, and the well layer has a narrower energy bandgap than the barrier layer;

a mask layer disposed in the first-conductivity-type semiconductor layer;

a first electrode disposed on the first-conductivity-type semiconductor layer; and

a second electrode disposed on the second-conductivity-type semiconductor layer,

wherein the first-conductivity-type semiconductor layer is formed with at least one recess portion, wherein the mask layer includes a masking region, and a window region distinguished from the masking region, and the recess portion is formed at the first-conductivity-type semiconductor layer, corresponding to the window region,

wherein the light emitting structure is mesa-etched from the second-conductivity-type semiconductor layer to a part of the first-conductivity-type semiconductor layer, the first electrode is disposed on a surface of the first-conductivity-type semiconductor layer exposed by the mesa-etching,

wherein the mask layer is disposed in the first-conductivity-type semiconductor layer corresponding to the active layer, and the mask layer is disposed in an upper part than the surface of the first-conductivity-type semiconductor layer exposed by the mesa-etching,

wherein the recess portion is formed at a portion of an upper surface of the first-conductivity-type semiconductor layer where a threading dislocation from a lower portion of the light emitting structure reaches, and

wherein the masking region of the mask layer blocks at least a part of threading dislocations advancing toward a top of the light emitting structure.

2. The light emitting diode according to claim 1 , wherein the recess portion is disposed between the window region and the active layer.

3. The light emitting diode according to claim 1 , wherein the mask layer comprises at least one of SiO 2 or SiN.

4. The light emitting diode according to claim 1 , wherein the mask layer is patterned such that a horizontal section shape of the patterned mask layer has a predetermined shape.

5. The light emitting diode according to claim 4 , wherein the horizontal section shape of the mask layer comprises a lattice shape, a stripe shape, a circular shape, an oval shape, or a polygonal shape.

6. The light emitting diode according to claim 1 , wherein the light emitting structure is disposed over a substrate, and the substrate comprises a light extraction structure formed at a surface of the substrate, to which the light emitting structure is adjacent.

7. The light emitting diode according to claim 1 , further comprising:

a current spreading layer disposed between the light emitting structure and the second electrode.

8. The light emitting diode according to claim 1 , further comprising:

an electron blocking layer disposed between the active layer and the second-conductivity-type semiconductor layer.

9. The light emitting diode according to claim 1 , wherein the mask layer has a thickness of 0.01 to 1.5 μm.

10. The light emitting diode according to claim 1 , wherein the window region and the masking region have a width ratio of 1:0.1 to 10.

11. The light emitting diode according to claim 8 , wherein the electron blocking layer comprises AlGaN.

12. The light emitting diode according to claim 1 , wherein the recess portion comprises a V-pit shape, an inverted polygonal corn shape, or an inverted pyramid shape.

13. The light emitting diode according to claim 1 , wherein the active layer is formed with a recess portion corresponding to the recess portion of the first-conductivity-type semiconductor layer.

14. A light emitting diode comprising:

a light emitting structure including a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer;

a mask layer disposed in the first-conductivity-type semiconductor layer, the mask layer including a window region and a masking region;

a first electrode disposed on the first-conductivity-type semiconductor layer; and

a second electrode disposed on the second-conductivity-type semiconductor layer,

wherein the first-conductivity-type semiconductor layer includes at least one recess portion formed to vertically overlap the window region of the mask layer,

wherein the light emitting structure is mesa-etched from the second-conductivity-type semiconductor layer to a part of the first-conductivity-type semiconductor layer, the first electrode is disposed on a surface of the first-conductivity-type semiconductor layer exposed by the mesa-etching,

wherein the mask layer is disposed in the first-conductivity-type semiconductor layer corresponding to the active layer, and the mask layer is disposed in an upper part than the surface of the first-conductivity-type semiconductor layer exposed by the mesa-etching,

the recess portion is formed at the first-conductivity-type semiconductor layer at an area corresponding to the window region,

wherein the recess portion is formed at a portion of an upper surface of the first-conductivity-type semiconductor layer where threading dislocations reach after passing through the window region of the mask layer, and

wherein the masking region of the mask layer blocks at least a part of threading dislocations advancing toward the light emitting structure.

15. The light emitting diode according to claim 14 , wherein the light emitting structure is disposed on a substrate, and the threading dislocations advancing toward the light emitting structure while being formed at an interface between the substrate and the light emitting structure.

16. A light emitting device package comprising:

a package body;

first and second lead frames disposed on the package body; and

a light emitting diode disposed on the package body, and the light emitting diode being electrically connected to the first and second lead frames,

wherein the light emitting diode comprises:

a substrate,

a light emitting structure disposed on the substrate, the light emitting structure including a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer, wherein the first-conductivity-type semiconductor layer, the active layer, and the second-conductivity-type semiconductor layer are disposed to be adjacent to one another in a same direction, the active layer includes well and barrier layers alternately stacked at least one time, and the well layer has a narrower energy bandgap than the barrier layer,

a mask layer disposed in the first-conductivity-type semiconductor layer,

a first electrode disposed on the first-conductivity-type semiconductor layer, and

a second electrode disposed on the second-conductivity-type semiconductor layer,

wherein the first-conductivity-type semiconductor layer is formed with at least one recess portion,

wherein the light emitting structure is mesa-etched from the second-conductivity-type semiconductor layer to a part of the first-conductivity-type semiconductor layer, the first electrode is disposed on a surface of the first-conductivity-type semiconductor layer exposed by the mesa-etching,

wherein the mask layer is disposed in the first-conductivity-type semiconductor layer corresponding to the active layer, and the mask layer is disposed in an upper part than the surface of the first-conductivity-type semiconductor layer exposed by the mesa-etching,

wherein the mask layer includes a masking region, and a window region distinguished from the masking region, and the recess portion is formed at the first-conductivity-type semiconductor layer at an area corresponding to the window region and where threading dislocations reach after passing through the window region of the mask layer, and

wherein the masking region of the mask layer blocks at least a part of threading dislocations advancing toward a top of the light emitting structure.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2021
From: LG INNOTEK CO., LTD.
To: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
Reel/Frame 056366/0335 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2011
From: JUNG, MYUNG HOON; LIM, HYUN CHUL; KIM, SUL HEE; CHOI, RAK JUN
To: LG INNOTEK CO., LTD.
Reel/Frame 027386/0035 →
Priority Claims (1)
KR 10-2011-0089492 · Sep 5, 2011 · national
Continuity (1)
Related Publication 20120080660A1 · Apr 5, 2012