IP Library Granted Patent US 9,021,291
Granted Patent B2
US 9,021,291 · App. 13/325,746 · Granted Apr 28, 2015

Synchronous network

Inventor: Anthony Magee (Leeds, GB)
Assignee: ADVA Optical Networking SE
H04J3/0688H04L12/2697G06F11/0751G06F11/277G06F1/10H04J3/14H04L12/2642H04J3/0697H03L7/0898H03L7/099H03L7/18H03L2207/04H03L2207/06
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Quick Facts
Patent No.
US 9,021,291
App. No.
13/325,746
Granted
Apr 28, 2015
Kind
B2
Abstract

A network node of a synchronous network, wherein said network node comprises a timing circuit which recovers a reference clock from a reception signal received by said network node from an upstream network node of said synchronous network and uses the recovered reference clock for a transmission signal transmitted by said network node to a downstream network node of said synchronous network; and a clock stability monitoring circuit which monitors internal control parameters (CP) of said timing circuit to detect an instability of the reference clock distributed within said synchronous network.

Claims (32)

1. A network node of a synchronous network, comprising:

a timing circuit, which recovers a reference clock from a reception signal received by said network node from an upstream network node of said synchronous network and uses the recovered reference clock for a transmission signal transmitted by said network node to a downstream network node of said synchronous network; and

a clock stability monitoring circuit which monitors internal control parameters of said timing circuit to detect an instability of the reference clock distributed within said synchronous network,

wherein the timing circuit comprises a register in which dummy data is written with a reception clock rate and from which said dummy data is read with a transmission clock rate to detect said instability of the distributed reference clock.

2. The network node according to claim 1 ,

wherein said timing circuit comprises a phase locked loop circuit for recovery of said reference clock from said reception signal.

3. The network node according to claim 2 ,

wherein said phase locked loop circuit is an analogue PLL circuit or a digital PLL circuit.

4. The network node according to claim 1 ,

wherein said clock stability monitoring circuit, monitors the internal control parameters of said timing circuit, in the time domain and/or in the frequency domain.

5. The network node according to claim 1 ,

wherein the monitored control parameters are written into a control parameter table stored in a local memory of said network node.

6. The network node according to claim 1 ,

wherein the clock stability monitoring circuit generates an alarm message if a monitored control parameter is not within a predetermined normal operation range.

7. The network node according claim 1 ,

wherein the distributed reference clock is generated by a primary reference clock generator of said synchronous network.

8. The network node according claim 1 ,

wherein said control parameter table stored in the local memory of said network node is read out by a network management system of said synchronous network.

9. The network node according to claim 8 ,

wherein the network management system analyses the read out control parameters of the network node to identify a faulty entity within the network node causing a reference clock instability in said synchronous network.

10. The network node according to claim 1 further comprising an injection circuit provided to adapt at least one control parameter of the timing circuit of said network node to cause an observable change of the reference clock forwarded to a downstream network node of said synchronous network.

11. The network node according to claim 1 ,

wherein said network node is a synchronous Ethernet device or a 1588 Precision Time Protocol device.

12. A synchronous network comprising:

network nodes according to claim 1 ,

a primary reference clock generator for generating a primary reference clock distributed in said synchronous network, and

a network management system for analyzing the control parameters of the network nodes of said synchronous network in the time or frequency domain.

13. The synchronous network according to claim 12 ,

wherein at least one network node is connected to a base station of a mobile telephone network which receives the distributed reference clock from the synchronous network.

14. A method for detecting instability of a reference clock distributed within a synchronous network, comprising:

monitoring internal control parameters of a timing circuit adapted to recover the distributed reference clock within a network node of said synchronous network to detect the instability of the distributed reference clock,

wherein the timing circuit comprises a register in which dummy data is written with a reception clock rate and from which said dummy data is read with a transmission clock rate to detect said instability of the distributed reference clock.

Assignments (4)
CHANGE OF NAME Recorded Nov 14, 2023
From: ADVA OPTICAL NETWORKING SE
To: ADTRAN NETWORKS SE
Reel/Frame 065567/0165 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ADDRESS OF THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 029792 FRAME 0762. ASSIGNOR(S) HEREBY CONFIRMS THE CONVEYING PARTY: ADVA AG OPTICAL NETWORKING RECEIVING PARTY: ADVA OPTICAL NETWORKING SE. Recorded Oct 8, 2013
From: ADVA AG OPTICAL NETWORKING
To: ADVA OPTICAL NETWORKING SE
Reel/Frame 031372/0366 →
CHANGE OF NAME Recorded Feb 11, 2013
From: ADVA AG OPTICAL NETWORKING
To: ADVA OPTICAL NETWORKING SE
Reel/Frame 029792/0762 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2012
From: MAGEE, ANTHONY
To: ADVA AG OPTICAL NETWORKING
Reel/Frame 027750/0087 →
Priority Claims (1)
EP 11165061 · May 6, 2011 · regional
Continuity (1)
Related Publication 20120324270A1 · Dec 20, 2012