Method of manufacturing a semiconductor device having lower leakage current between semiconductor substrate and bit lines
View Patent ↗A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that are in contact with the side faces of a trapping layer in the ONO film over the portions of the bit line located on both sides of the silicide layer, the sidewalls being formed with silicon oxide films including phosphorus.
1. A method of manufacturing a semiconductor device comprising:
forming a trapping layer on a semiconductor substrate;
forming an opening in the trapping layer;
forming a bit line in a portion of the opening located within the semiconductor substrate;
forming sidewalls on side faces of the opening, the sidewalls being formed with oxide silicon films including phosphorus; and
forming a silicide layer in the bit line, with the sidewalls serving as masks and wherein the top surface of the silicide layer is fully covered over a span from a first inside surface to a second inside surface of the sidewalls by a single structure formed of a single insulating material.
2. The method as claimed in claim 1 , further comprising forming a top oxide film on the trapping layer, the sidewalls, and the silicide layer.
3. The method as claimed in claim 2 , further comprising forming a word line on the top oxide film, the word line extending in a width direction of the bit line.
4. The method as claimed in claim 1 , further comprising forming a top oxide film on the trapping layer, wherein:
forming the opening includes forming the opening in the top oxide film and the trapping layer; and
forming the sidewalls includes forming the sidewalls on side faces of the opening formed in the top oxide film and the trapping layer.
5. The method as claimed in claim 4 , further comprising forming a first conductive layer to be a gate electrode on the top oxide film, wherein:
forming the opening includes forming the opening in the first conductive layer, the top oxide film, and the trapping layer; and
forming the sidewalls includes forming the sidewalls on side faces of the opening formed in the first conductive layer, the top oxide film, and the trapping layer.
6. The method as claimed in claim 5 , further comprising:
forming a second conductive layer to be a word line on the first conductive layer; and
forming the word line from the second conductive layer and the gate electrode from the first conductive layer by removing predetermined regions of the second conductive layer and the first conductive layer.
7. The method as claimed in claim 6 , further comprising forming an insulating film on the first conductive layer, wherein forming the silicide layer includes: forming a metal layer on the insulating film and the bit line located in the opening; and siliciding the metal layer through a heat treatment.
8. The method as claimed in claim 6 , further comprising forming an insulating layer in the opening, wherein forming the second conductive layer includes forming the second conductive layer on the first conductive layer and the insulating layer.
9. The method as claimed in claim 1 , further comprising:
forming an interlayer insulating film on the trapping layer; and
forming a contact portion in the interlayer insulating film, the contact portion connecting to the silicide layer.