IP Library Granted Patent US 8,625,654
Granted Patent B2
US 8,625,654 · App. 13/326,185 · Granted Jan 7, 2014

Pulse generator of UWB system

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Quick Facts
Patent No.
US 8,625,654
App. No.
13/326,185
Granted
Jan 7, 2014
Kind
B2
Abstract

A pulse generator of an ultra wideband (UWB) system includes: a plurality of delay cells for receiving pulses, delaying the received pulses for a predetermined time, and outputting the delayed pulses; and an edge combiner connected to output ends of the plurality of delay cells for receiving the delayed pulses from the plurality of delay cells, outputting fine pulses corresponding to the delayed time, and generating one impulse signal with the outputted fine pulses. The edge combiner includes a plurality of XOR gates for receiving a first delayed pulse and a second delayed pulse from an n th delay cell and an (n+1) th delay cell among the plurality of delay cells and generating fine pulses, respectively, and an OR gate for receiving a first fine pulse and a second fine pulse respectively output from a first XOR gate and a second XOR gate included in the plurality of XOR gates.

Claims (20)

1. A pulse generator of an ultra wideband (UWB) system, comprising:

a plurality of delay cells for receiving pulses, delaying the received pulses for a predetermined time, and outputting the delayed pulses; and

an edge combiner connected to output ends of the plurality of delay cells for receiving the delayed pulses from the plurality of delay cells, outputting fine pulses corresponding to the delayed time, and generating one impulse signal with the outputted fine pulses,

wherein the edge combiner includes:

a plurality of XOR gates for receiving a first delayed pulse and a second delayed pulse from an n th delay cell and an (n+1) th delay cell among the plurality of delay cells and generating fine pulses, respectively; and

an OR gate for receiving a first fine pulse and a second fine pulse respectively output from a first XOR gate and a second XOR gate included in the plurality of XOR gates and generating one impulse signal with the first fine pulse and the second file pulse.

2. The pulse generator of claim 1 , wherein the edge combiner further comprises

an AND gate connected to output ends of predetermined delay cells among the plurality of delay cells for controlling outputting delayed pulses from the connected delay cells to the XOR gate according to a control signal input with the pulse.

3. The pulse generator of claim 2 , wherein the AND gate controls the pulse generator to transmit a signal from one of first to third channels.

4. The pulse generator of claim 1 , wherein the XOR gate selects one generated first from two fine pulses generated from the first delayed pulse and the second delayed pulse and outputs the selected one.

5. A pulse generator of an ultra wideband (UWB) system, comprising:

a channel setup unit for controlling a number of fine pulses to be output in order to select a channel to transmit a signal according to a control signal input with a pulse; and

an AND gate unit for receiving fine pulses output from the channel setup unit and generating one impulse signal with the received fine pulses,

wherein the channel setup unit includes:

a plurality of delay cells for delaying input pulses for a predetermined time and outputting delayed pulses; and

a plurality of XOR gates for receiving a first delayed pulse and a second delayed pulse output from an n th delay cell and an (n+1) th delay cell among the plurality of delay cells and generating fine pulses.

6. The pulse generator of claim 5 , wherein the channel setup unit includes an AND gate connected to output ends of predetermined delay cells among the plurality of delay cells and controlling outputting of the delayed pulses from the connected delay cells to the XOR gate.

7. The pulse generator of claim 6 , wherein the channel setup unit includes a first channel setup unit, a second channel setup unit, and a third channel setup unit,

wherein the first channel setup unit includes a plurality of delay cells and a plurality of XOR gates connected to output ends of the plurality of delay cells, and

wherein the second channel setup unit and the third channel setup unit include a plurality of delay cells, a plurality of AND gates connected to output ends of the plurality of delay cells, and an XOR gate connected to output ends of the plurality of AND gates.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2016
From: ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY
To: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
Reel/Frame 038238/0905 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2016
From: UNIST ACADEMY-INDUSTRY RESEARCH CORPORATION
To: ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY
Reel/Frame 037771/0538 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2011
From: JEONG, JIN DOO; LEE, HYUNG SOO; CHOI, SANGSUNG; BIEN, FRANKLIN; CHOI, YUN HO; KIM, YOUNG SU
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE; UNIST ACADEMY-INDUSTRY RESEARCH CORPORATION
Reel/Frame 027397/0277 →