IP Library Granted Patent US 8,564,371
Granted Patent B2
US 8,564,371 · App. 13/326,443 · Granted Oct 22, 2013

Amplification circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,564,371
App. No.
13/326,443
Granted
Oct 22, 2013
Kind
B2
Abstract

An amplification circuit, which may be in a receive path of a communication device, includes an amplifier including at least a first amplification device and a switchable attenuation circuit. The switchable attenuation circuit includes one or more switches and a plurality of attenuation devices and is operable to provide different levels of attenuation to an input signal prior to input to the amplifier depending on the status of the one or more switches. The attenuation devices may be capacitors, wherein the capacitors may be arranged to form a capacitive divider with a level of attenuation dependent on the status of the switches. The switchable attenuation circuit may be a switched capacitive attenuation ladder of n stages, n being any integer, each ladder stage including a capacitive divider. The amplification circuit may also include a switch, which when closed provides an unattenuated path for the input signal to the amplifier input.

Claims (48)

1. An amplification circuit comprising;

an amplifier including at least a first amplification device; and

a switchable attenuation circuit;

wherein the switchable attenuation circuit comprises one or more switches and a plurality of attenuation devices and is operable to provide different levels of attenuation to an input signal prior to input to the amplifier depending on the status of the one or more switches, wherein the switchable attenuation circuit further comprises a switch which when closed provides an unattenuated path for the input signal to the amplifier input.

2. The amplification circuit of claim 1 , wherein the attenuation devices are capacitors.

3. The amplification circuit of claim 2 wherein the capacitors are arranged to form a capacitive divider with a level of attenuation dependent on the status of the switches.

4. The amplification circuit of claim 1 , wherein the switchable attenuation circuit comprises a switched capacitive attenuation ladder of n stages, n being any integer, each ladder stage including a capacitive divider formed by two capacitors, and a switch for selective connection of the output of each divider to the amplifier input, the circuit being operable such that no more than one switch is closed at any time, the attenuation applied to the input signal being dependent on which of the switches is closed.

5. The amplification circuit of claim 1 , wherein the switchable attenuation circuit comprises a plurality of capacitors in parallel between an input of the switchable attenuation circuit and the input of the amplifier and a plurality of capacitors in parallel between an input of the amplifier and ground or other reference node, each capacitor having a switch in series with it, the attenuation applied to the input signal being dependent on the combination of switches closed.

6. The amplification circuit of claim 1 , wherein the amplifier comprises a second input, the amplification circuit provides substantially no attenuation for the second input.

7. The amplification circuit of claim 6 , wherein the second input comprises a second amplification device in the amplifier, the amplification circuit being operable such that the second amplification device is made selectively by-passable.

8. The amplification circuit of claim 7 , wherein:

when an input signal is above a predetermined threshold, the second amplification device is bypassed and the input signal undergoes attenuation by the switchable attenuation circuit, prior to amplification via the first input; and

when an input signal is below a predetermined threshold, the second amplification device is not bypassed and the input signal is amplified via the second input without prior attenuation.

9. The amplification circuit of claim 8 , wherein the first input is disconnected from the amplification circuit input, the first amplification device becomes a cascode device for the second amplification device.

10. The amplification circuit of claim 1 , wherein the amplification circuit operates differentially.

11. The amplification circuit of claim 1 , further comprising a control circuit for control of the switchable attenuation circuit and amplifier.

12. The amplification circuit of claim 11 , wherein the control circuit comprises part of an automatic gain control circuit.

13. The amplification circuit of claim 1 , further comprising an impedance matching circuit at its input(s).

14. A communication device comprising:

processing circuitry;

memory coupled to the processing circuitry; and

a communication interface coupled to the processing circuitry having a receive path having an amplifier comprising:

at least a first amplification device;

a switchable attenuation circuit;

wherein the switchable attenuation circuit comprises one or more switches and a plurality of attenuation devices and is operable to provide different levels of attenuation to an input signal prior to a first input to the amplifier depending on the status of the one or more switches; and

wherein the amplifier comprises a second input, the amplifier providing substantially no attenuation for the second input.

15. The communication device of claim 14 , wherein the communication interface comprises one or more of:

Power Line Communication (PLC) interface:

a Local Area Network (LAN) interface;

a Wireless Wide Area Network (WWAN) interface;

a Wireless Local Area Network (WLAN) interface;

a coaxial interface;

a millimeter wave interface;

a cellular telephony interface;

a Near Field Communication (NFC) standard;

an infrared interface; and

an optical interface.

16. The communication device of claim 14 , wherein the switchable attenuation circuit comprises a switched capacitive attenuation ladder of n stages, n being any integer, each ladder stage including a capacitive divider formed by two capacitors, and a switch for selective connection of the output of each divider to the amplifier input, the circuit being operable such that no more than one switch is closed at any time, the attenuation applied to the input signal being dependent on which of the switches is closed.

17. The communication device of claim 14 , wherein the switchable attenuation circuit comprises a plurality of capacitors in parallel between an input of the switchable attenuation circuit and the input of the amplifier and a plurality of capacitors in parallel between an input of the amplifier and ground or other reference node, each capacitor having a switch in series with it, the attenuation applied to the input signal being dependent on the combination of switches closed.

18. The communication device of claim 14 , wherein the switchable attenuation circuit further comprises a switch which when closed provides an unattenuated path for the input signal to the amplifier input.

19. The communication device of claim 14 , wherein the second input comprises a second amplification device in the amplifier such that the second amplification device is made selectively by-passable.

20. The communication device of claim 19 , wherein:

when an input signal is above a predetermined threshold, the second amplification device is bypassed and the input signal undergoes attenuation by the switchable attenuation circuit, prior to amplification via the first input; and

when an input signal is below a predetermined threshold, the second amplification device is not bypassed and the input signal is amplified via the second input without prior attenuation.

21. An amplification circuit comprising;

an amplifier including at least a first amplification device; and

a switchable attenuation circuit configured to provide different levels of attenuation to an input signal prior to input to the amplifier and comprising a plurality of capacitors in parallel between an input of the switchable attenuation circuit and the input of the amplifier and a plurality of capacitors in parallel between an input of the amplifier and ground or other reference node, each capacitor having a switch in series with it, the attenuation applied to the input signal being dependent on the combination of switches closed.

22. The amplification circuit of claim 21 , further comprising a control circuit for control of the switchable attenuation circuit and amplifier.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2011
From: TRULLS FORTUNY, XAVIER; MATEO PENA, DIEGO; BOFILL-PETIT, ADRIA
To: BROADCOM CORPORATION
Reel/Frame 027396/0388 →