Granted Patent B2

US 8,671,250 · App. 13/327,326 · Granted Mar 11, 2014

Abstract

Claims (93)

1. A data storage device comprising:

a non-volatile memory comprising a plurality of memory segments; and control circuitry operable to:

receive a write command comprising a first logical block address (LBA) and first user data, and a second LBA and second user data;

map the first LBA to a first physical block address (PBA) for addressing a first memory segment;

map the second LBA to a second PBA for addressing a second memory segment;

generate first redundancy in response to the first user data;

generate second redundancy in response to the second user data;

generate parity data in response to the first and second user data;

generate third redundancy in response to:

at least one of the first LBA and the first PBA; and

at least one of the second LBA and the second PBA; and

write the first and second user data and parity data to the non-volatile memory and write the first, second, and third redundancy to the non-volatile memory.

2. The data storage device as recited in claim 1 , wherein the control circuitry is operable to:

generate the first redundancy in response to the first user data and at least one of the first LBA and the first PBA; and

generate the second redundancy in response to the second user data and at least one of the second LBA and the second PBA.

3. The data storage device as recited in claim 2 , wherein the control circuitry is operable to generate the third redundancy in response to the first redundancy and the second redundancy.

4. The data storage device as recited in claim 1 , wherein the control circuitry is further operable to:

receive a read command comprising the first and second LBAs;

read the first user data and first redundancy from the non-volatile memory;

correct errors in the first user data using the first redundancy;

read the second user data and second redundancy from the non-volatile memory;

correct errors in the second user data using the second redundancy; and

when the second user data is uncorrectable using the second redundancy:

read the parity data and the third redundancy from the non-volatile memory;

verify the parity data using the third redundancy; and

regenerate the second user data using the first user data and the parity data.

5. The data storage device as recited in claim 4 , wherein the control circuitry is operable to:

generate the first redundancy in response to the first user data and at least one of the first LBA and the first PBA;

generate the second redundancy in response to the second user data and at least one of the second LBA and the second PBA;

correct the first user data in response to the first redundancy and at least one of the first LBA and the first PBA; and

correct the second user data in response to the second redundancy and at least one of the second LBA and the second PBA.

6. The data storage device as recited in claim 1 , wherein the control circuitry is operable to:

combine the first and second LBAs to generate metadata; and

generate the third redundancy in response to the parity data and the metadata.

7. The data storage device as recited in claim 6 , wherein the control circuitry is operable to:

combine the first and second LBAs to regenerate the metadata; and

verify the parity data using the third redundancy and the regenerated metadata.

8. The data storage device as recited in claim 1 , wherein the control circuitry is operable to:

combine the first and second PBAs to generate metadata; and

generate the third redundancy in response to the parity data and the metadata.

9. The data storage device as recited in claim 8 , wherein the control circuitry is operable to:

combine the first and second PBAs to regenerate the metadata; and

verify the parity data using the third redundancy and the regenerated metadata.

10. The data storage device as recited in claim 1 , wherein the control circuitry is operable to generate the third redundancy in response to:

at least one of the first LBA and the first PBA;

at least one of the second LBA and the second PBA; and

at least one of a third LBA and a third PBA for storing the parity data to a third memory segment.

11. A method of operating a data storage device comprising a non-volatile memory comprising a plurality of memory segments, the method comprising:

receiving a write command comprising a first logical block address (LBA) and first user data, and a second LBA and second user data;

mapping the first LBA to a first physical block address (PBA) for addressing a first memory segment;

mapping the second LBA to a second PBA for addressing a second memory segment;

generating first redundancy in response to the first user data;

generating second redundancy in response to the second user data;

generating parity data in response to the first and second user data;

generating third redundancy in response to:

at least one of the first LBA and the first PBA; and

at least one of the second LBA and the second PBA; and

writing the first and second user data and parity data to the non-volatile memory and write the first, second, and third redundancy to the non-volatile memory.

12. The method as recited in claim 11 , further comprising:

generating the first redundancy in response to the first user data and at least one of the first LBA and the first PBA; and

generating the second redundancy in response to the second user data and at least one of the second LBA and the second PBA.

13. The method as recited in claim 12 , further comprising generating the third redundancy in response to the first redundancy and the second redundancy.

14. The method as recited in claim 11 , further comprising:

receiving a read command comprising the first and second LBAs;

reading the first user data and first redundancy from the non-volatile memory;

correcting errors in the first user data using the first redundancy;

reading the second user data and second redundancy from the non-volatile memory;

correcting errors in the second user data using the second redundancy; and

when the second user data is uncorrectable using the second redundancy:

reading the parity data and the third redundancy from the non-volatile memory;

verifying the parity data using the third redundancy; and

regenerating the second user data using the first user data and the parity data.

15. The method as recited in claim 14 , further comprising:

generating the first redundancy in response to the first user data and at least one of the first LBA and the first PBA;

generating the second redundancy in response to the second user data and at least one of the second LBA and the second PBA;

correcting the first user data in response to the first redundancy and at least one of the first LBA and the first PBA; and

correcting the second user data in response to the second redundancy and at least one of the second LBA and the second PBA.

16. The method as recited in claim 11 , further comprising:

combining the first and second LBAs to generate metadata; and

generating the third redundancy in response to the parity data and the metadata.

17. The method as recited in claim 16 , further comprising:

combining the first and second LBAs to regenerate the metadata; and

verifying the parity data using the third redundancy and the regenerated metadata.

18. The method as recited in claim 11 , further comprising:

combining the first and second PBAs to generate metadata; and

generating the third redundancy in response to the parity data and the metadata.

19. The method as recited in claim 18 , further comprising:

combining the first and second PBAs to regenerate the metadata; and

verifying the parity data using the third redundancy and the regenerated metadata.

20. The method as recited in claim 11 , further comprising generating the third redundancy in response to:

at least one of the first LBA and the first PBA;

at least one of the second LBA and the second PBA; and

at least one of a third LBA and a third PBA for storing the parity data to a third memory segment.

Assignments (8)