Communication system, and corresponding integrated circuit and method
View Patent ↗A communication system includes interfacing between a first synchronous circuit and a second synchronous circuit. The system includes a first interface system and a second interface system. The first interface system receives data from the first synchronous circuit, and encodes the data according to an asynchronous communication protocol. The encoded data are transmitted over a communication channel to the second interface system. The second interface system decodes the data and transmits the decoded data to the second synchronous circuit. The first interface system includes a first FIFO memory for storing temporarily the data received from the first synchronous circuit and the second interface system includes a second FIFO memory for storing temporarily the data transmitted over the communication channel.
1. A communication system for interfacing a first synchronous circuit with a second synchronous circuit comprising:
a first interface system configured for:
a) receiving data from said first synchronous circuit according to a synchronous communication protocol;
b) converting said data received from said first synchronous circuit in data encoded according to an asynchronous communication protocol; and
c) transmitting said encoded data over a communication channel;
a second interface system configured for:
a) receiving said data transmitted over said communication channel;
b) converting said data transmitted over said communication channel in data decoded according to said asynchronous communication protocol; and
c) transmitting said decoded data to said second synchronous circuit, wherein said first interface system comprises a first first-in first-out memory for storing temporarily said data received from said first synchronous circuit and said second interface system comprises a second first-in first-out memory for storing temporarily said data transmitted over said communication channel, and wherein said communication system is configured for transmitting to said first synchronous circuit a control signal determined as a function of the state of said first and said second memory such that the first synchronous circuit in communication with, in the first interface system, a converter and the first first-in first-out memory, provides the asynchronous data, and the asynchronous data is received by the second first-in first-out memory in the second interface system, together with a second converter circuit, which in turn is in communication with the second synchronous circuit.
2. The system of claim 1 , wherein said control signal comprises an acknowledge signal, which signals to said first synchronous circuit the fact that said first interface system has received said data from said first synchronous circuit.
3. The system of claim 2 , wherein said control signal comprises a binary signal, and wherein said communication system is configured for changing the logic value of said control signal, when said first interface system has received said data from said first synchronous circuit and each of said first and said second memory comprises at least one free memory location.
4. The system of claim 3 , wherein said communication system is configured for:
a) managing a first read pointer indicating the memory location from which data temporarily stored in said first memory is read; and
b) determining the state of said first memory as a function of said first read pointer.
5. The system of claim 3 , wherein said communication system is configured for:
a) managing a second read pointer indicating the memory location from which data temporarily stored in said second memory is read; and
b) determining the state of said second memory as a function of said second read pointer.
6. The system of claim 1 , further comprising a stage of an asynchronous pipeline between said first and said second interface system, wherein said stage is configured for receiving and forwarding said encoded data from said first interface system and to said second interface system, wherein said stage comprises a third first-In first-Out memory for storing temporarily said data to be forwarded to said second interface system.
7. The system of claim 6 , wherein said second and said third memory have the same number of memory locations.
8. The system of claim 6 , wherein said second and said third memory have a different number of memory locations, and wherein said communication system is configured for determining said control signal as a function of the state of said third memory.
9. An integrated circuit comprising a first synchronous circuit, a second synchronous circuit, and a communication system for interfacing said first synchronous circuit with said second synchronous circuit, wherein said communication system comprises:
a first interface system configured for:
a) receiving data from said first synchronous circuit according to a synchronous communication protocol;
b) converting said data received from said first synchronous circuit in data encoded according to an asynchronous communication protocol; and
c) transmitting said encoded data over a communication channel;
a second interface system configured for:
a) receiving said data transmitted over said communication channel;
b) converting said data transmitted over said communication channel in data decoded according to said asynchronous communication protocol; and
c) transmitting said decoded data to said second synchronous circuit, wherein said first interface system comprises a first first-in first-out memory for storing temporarily said data received from said first synchronous circuit and said second interface system comprises a second first-in first-out memory for storing temporarily said data transmitted over said communication channel, and wherein said communication system is configured for transmitting to said first synchronous circuit a control signal determined as a function of the state of said first and said second memory such that the first synchronous circuit in communication with, in the first interface system, a converter and the first first-in first-out memory, provides the asynchronous data, and the asynchronous data is received by the second first-in first-out memory in the second interface system, together with a second converter circuit, which in turn is in communication with the second synchronous circuit.
10. The integrated circuit of claim 9 , wherein said control signal comprises an acknowledge signal, which signals to said first synchronous circuit the fact that said first interface system has received said data from said first synchronous circuit.
11. The integrated circuit of claim 10 , wherein said control signal comprises a binary signal, and wherein said communication system is configured for changing the logic value of said control signal, when said first interface system has received said data from said first synchronous circuit and each of said first and said second memory comprises at least one free memory location.
12. The integrated circuit of claim 11 , wherein said communication system is configured for:
a) managing a first read pointer indicating the memory location from which data temporarily stored in said first memory is read; and
b) determining the state of said first memory as a function of said first read pointer.
13. The integrated circuit of claim 11 , wherein said communication system is configured for:
a) managing a second read pointer indicating the memory location from which data temporarily stored in said second memory is read; and
b) determining the state of said second memory as a function of said second read pointer.
14. The integrated circuit of claim 9 , further comprising a stage of an asynchronous pipeline between said first and said second interface system, wherein said stage is configured for receiving and forwarding said encoded data from said first interface system and to said second interface system, wherein said stage comprises a third first-In first-Out memory for storing temporarily said data to be forwarded to said second interface system.
15. The integrated circuit of claim 14 , wherein said second and said third memory have the same number of memory locations.
16. The integrated circuit of claim 14 , wherein said second and said third memory have a different number of memory locations, and wherein said communication system is configured for determining said control signal as a function of the state of said third memory.
17. A communication method for interfacing a first synchronous circuit with a second synchronous circuit comprising:
receiving data from said first synchronous circuit according to a synchronous communication protocol;
converting said data received from said first synchronous circuit in data encoded according to an asynchronous communication protocol;
transmitting said encoded data (ADATA) over a communication channel;
receiving said data transmitted over said communication channel;
converting said data transmitted over said communication channel in data decoded according to said asynchronous communication protocol;
transmitting said decoded data to said second synchronous circuit; and
storing temporarily said data received from said first synchronous circuit in a first memory and storing temporarily said data transmitted over said communication channel in a second memory such that the first synchronous circuit in communication with a converter and the first memory, provides the asynchronous data, and the asynchronous data is received by the second memory together with a second converter circuit, which in turn is in communication with the second synchronous circuit.
18. The method of claim 17 wherein said first memory comprises a first-in first-out memory.
19. The method of claim 17 wherein said second memory comprises a first-in first-out memory.
20. The method of claim 17 further comprising transmitting to said first synchronous circuit a control signal determined as a function of the state of said first and said second memory.