Memory access control circuit, prefetch circuit, memory device and information processing system
View Patent ↗Disclosed herein is a memory access control circuit including: a determination section adapted to determine whether a target requested by a first wraparound memory access request from a processor is stored in a prefetch buffer; a request generation section adapted to generate a second wraparound memory access request including the target if it is determined that the target is not stored in the prefetch buffer; and an address conversion section adapted to convert the start address of the first wraparound memory access request according to predetermined rules for use as a start address of the second wraparound memory access request.
1. A memory access control circuit comprising:
one or more processors operable to:
determine whether a target, requested by a first wraparound memory access request by the one or more processors to a memory, is stored in a prefetch buffer; generate a second wraparaound memory access request, by the prefetch buffer to the memory, including the target based on determining that the target is not stored in the prefetch buffer;
and covert a start address of the first wraparound memory access request for use as a start address of the second wraparound memory access request in an event a wraparound size of the first wraparound memory access request by the one or more processors is different from a wraparound size of the second wraparound memory access request by the prefetch buffer;
wherein the wraparound size of the one or more processors is 2 m bursts, and m bits starting from the least significant bit of the start address of the first wraparound memory access request are replaced with zeroes to generate the start address of the second wraparound memory access request, wherein a value of m is based on the wraparound size of the first memory access request.
2. The memory access control circuit of claim 1 , wherein if the first wraparound memory access request is intended to request a four-burst wraparound, and if the second wraparound memory access request is intended to request a sixteen-burst wraparound, the one or more processors are operable to convert the start address of the first wraparound memory access request by replacing the lower two bits of the unit of burst of the start address of the first wraparound memory access request with zeroes.
3. The memory access control circuit of claim 1 , wherein if the first wraparound memory access request is to request a four-burst wraparound, and if the second wraparound memory access request is to request an eight-burst wraparound, the one or more processors are operable to convert the start address of the first wraparound memory access request by replacing the lower two bits of the unit of burst of the start address of the first wraparound memory access request with zeroes.
4. The memory access control circuit of claim 1 , wherein if the first wraparound memory access request is to request an eight-burst wraparound, and if the second wraparound memory access request is to request a sixteen-burst wraparound, the one or more processors are operable to convert the start address of the first wraparound memory access request by replacing the lower three bits of the unit of burst of the start address of the first wraparound memory access request with zeroes.
5. A prefetch circuit comprising:
a prefetch buffer; and
one or more processors operable to:
determine whether a target, requested by a first wraparound memory access request by the one or more processors to a memory, is stored in the prefetch buffer;
generate a second wraparound memory access request, by the prefetch buffer to the memory, including the target based on determining that the target is not stored in the prefetch buffer; and
convert a start address of the first wraparound memory access request according to predetermined ruled for use as a start address of the second wraparound memory access request in an event a wraparound size of the first wraparound memory access request by the one or more processors is different from a wraparound size of the second wraparound memory access request by the prefetch buffer,
wherein the wraparound size of the one or more processors is 2 m bursts, and m bits starting from the least significant bit of the start address of the first wraparound memory access request are replaced with zeroes to generate the start address of the second wraparound memory access request, wherein a value of m is based on the wraparound size of the first memory access request.
6. A memory device comprising:
a memory;
a prefetch buffer adapted to store a copy of a part of the memory; and
one or more processors operable to:
determine whether a target, requested by a first wraparound memory access request by the one or more processors to the memory, is stored in the prefetch buffer;
generate a second wraparound memory access request, by the prefetch buffer to the memory, including the target to the memory based on determining that the target is not stored in the prefetch buffer; and
convert the start address of the first wraparound memory access request according to predetermined rules for use as a start address of the second wraparound memory access request in an event a wraparound size of the first wraparound memory access request by the one or more processors is different from a wraparound size of the second wraparound memory access request by the prefetch buffer,
wherein the wraparound size of the one or more processors is 2 m bursts, and m bits starting from the least significant bit of the start address of the first wraparound memory access request are replaced with zeroes to generate the start address of the second wraparound memory access request, wherein a value of m is based on the wraparound size of the first memory access request.
7. An information processing system comprising:
a memory;
a prefetch buffer adapted to store a copy of part of the memory;
one or more processors operable to:
determine whether a target, requested by a first wraparound memory access request by the one or more processors to the memory, is stored in the prefetch buffer;
generate a second wraparound memory access request, by the prefetch buffer to the memory, including the target to the memory based on determining that the target is not stored in the prefetch buffer; and
convert a start address of the first wraparound memory access request for use as a start address of the second wraparound memory access request in an event a wraparound size of the first wraparound memory access request by the one or more processors is different from a wraparound size of the second wraparound memory access request by the prefetch buffer,
wherein the wraparound size of the one or more processors is 2 m bursts, and m bits starting from the least significant bit of the start address of the first wraparound memory access request are replaced with zeroes to generate the start address of the second wraparound memory access request, wherein a value of m is based on the wraparound size of the first memory access request.
8. The memory access circuit of claim 1 , wherein the one or more processors are operable to manage address tags of targets stored in the prefetch buffer.
9. The memory access circuit of claim 1 , wherein the one or more processors are operable to determine whether the target of a memory access request is stored in the prefetch buffer.
10. The memory access circuit of claim 1 , wherein the conversion is based on a transfer burst length for the second wraparound memory access request, the transfer burst length being based on a previous transfer burst length for the first wraparound memory access request.