IP Library Granted Patent US 8,823,344
Granted Patent B2
US 8,823,344 · App. 13/328,775 · Granted Sep 2, 2014

Control circuit, electronic device, and method for controlling power supply

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Quick Facts
Patent No.
US 8,823,344
App. No.
13/328,775
Granted
Sep 2, 2014
Kind
B2
Abstract

A control circuit arranged in a power supply including first and second switches to control an output voltage of the power supply. The control circuit includes a first control circuit that switches the first and second switches in a complementary manner in accordance with a comparison result of a first reference voltage and a feedback voltage corresponding to the output voltage of the power supply. A first comparison circuit compares the output voltage or feedback voltage with a second reference value. A second comparison circuit compares a coupling point current flowing through a coupling point between the first and second switches with a third reference value. A second control circuit disables complementary switching of the first and second switches in accordance with an output signal from the first comparison circuit and enables the complementary switching in accordance with an output signal of the second comparison circuit.

Claims (38)

1. A control circuit comprising:

a first control circuit coupled to a first switch and a second switch of a power supply, wherein the first control circuit is configured to switch the first switch and a second switch in a complementary manner in accordance with a comparison result of a first reference voltage and a voltage value of a feedback voltage corresponding to an output voltage of the power supply;

a first comparison circuit configured to compare one of a voltage value of the output voltage and the voltage value of the feedback voltage with a second reference value; and

a second comparison circuit configured to compare a current value of a coupling point current flowing through a point between the first switch and the second switch with a third reference value; and

a second control circuit configured to disable complementary switching of the first switch and the second switch and configured to inactivate the second switch in accordance with an output signal from the first comparison circuit, wherein the second control circuit enables the disabled complementary switching in accordance with an output signal of the second comparison circuit.

2. The control circuit according to claim 1 , wherein the second comparison circuit compares a voltage value at the coupling point with a fourth reference value and determines whether the coupling point current has reached the third reference value.

3. The control circuit according to claim 1 , further comprising:

a reverse current detection circuit configured to inactivate the second switch when detecting reverse flow of the coupling point current toward an input side; and

a third control circuit configured to invalidate an output of the reverse current detection circuit at least for a certain period from when the disabled complementary switching is enabled.

4. The control circuit according to claim 3 , wherein the certain period is a period from when the disabled complementary switching is enabled to when the reverse current of the coupling point current is detected.

5. The control circuit according to claim 3 , wherein the third control circuit includes a signal generation circuit configured to generate a signal for invalidating an output of the reverse current detection circuit from when the complementary switching is disabled to when the reverse flow of the coupling point current is detected after the disabled complementary switching is enabled.

6. The control circuit according to claim 3 , wherein the third control circuit includes a signal generation circuit configured to generate a signal for invalidating the output of the reverse current detection circuit until a certain period elapses from when the disabled complementary switching is enabled after the complementary switching is disabled.

7. The control circuit according to claim 1 , wherein

the first comparison circuit configured to generate a first detection signal when the voltage value of the output voltage reaches the second reference value that is greater than a target value of the output voltage,

the second comparison circuit configured to generate a second detection signal when the current value of the coupling point current reaches the third reference value of 0 A, and

the second control circuit configured to disable the complementary switching in response to the first detection signal and enables the disablement of the complementary switching in response to the second detection signal.

8. An electronic device comprising:

a power supply including a first switch, a second switch, and a control circuit; and

an internal circuit supplied with an output voltage of the power supply, wherein the control circuit includes:

a first control circuit configured to switch the first switch and the second switch of the power supply in a complementary manner in accordance with a comparison result of a first reference value and a voltage value of a feedback voltage corresponding to the output voltage of the power supply,

a first comparison circuit configured to compare one of a voltage value of the output voltage and the voltage value of the feedback voltage with a second reference value,

a second comparison circuit configured to compare a current value of a coupling point current flowing through a point between the first switch and the second switch with a third reference value,

a second control circuit configured to disable complementary switching of the first switch and the second switch and configured to inactivate the second switch in accordance with an output signal from the first comparison circuit, wherein the second control circuit enables the disabled complementary switching in accordance with an output signal from the second comparison circuit.

9. The electronic device according to claim 8 , wherein the second comparison circuit compares a voltage value at the coupling point with a fourth reference value and determines whether the coupling point current has reached the third reference value.

10. The control circuit according to claim 8 , further comprising:

a reverse current detection circuit configured to inactivate the second switch when detecting reverse flow of the coupling point current toward an input side; and

a third control circuit configured to invalidate an output of the reverse current detection circuit at least for a certain period from when the disabled complementary switching is enabled.

11. The control circuit according to claim 10 , wherein the certain period is a period from when the disabled complementary switching is enabled to when the reverse current of the coupling point current is detected.

12. The control circuit according to claim 10 , wherein the third control circuit includes a signal generation circuit configured to generate a signal for invalidating an output of the reverse current detection circuit from when the complementary switching is disabled to when the reverse flow of the coupling point current is detected after the disabled complementary switching is enabled.

13. The control circuit according to claim 10 , wherein the third control circuit includes a signal generation circuit configured to generate a signal for invalidating the output of the reverse current detection circuit until a certain period elapses from when the disabled complementary switching is enabled after the complementary switching is disabled.

14. The electronic device according to claim 8 , wherein:

the first comparison circuit configured to generate a first detection signal when the voltage value of the output voltage reaches the second reference value that is greater than a target value of the output voltage,

the second comparison circuit configured to generate a second detection signal when the current value of the coupling point current reaches the third reference value of 0 A, and

the second control circuit configured to disable the complementary switching in response to the first detection signal and enables the disablement of the complementary switching in response to the second detection signal.

15. A method for controlling a power supply comprising:

switching a first switch and a second switch of a power supply in a complementary manner in accordance with a comparison result of a first reference value and a voltage value of a feedback voltage corresponding to an output voltage of the power supply;

disabling complementary switching of the first switch and the second switch and inactivating the second switch when one of a voltage value of the output voltage and the voltage value of the feedback voltage reaches a second reference value that is greater than a target value of the output voltage; and

enabling the disabled complementary switching when a current value of a coupling point current flowing through a point between the first switch and the second switch reaches a third reference value.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2021
From: MUFG UNION BANK, N.A.,
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 057501/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 052487/0808 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2020
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 052410/0691 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 11, 2012
From: KUSHIDA, KOICHIRO; FUTAMURA, KAZUYOSHI; KUMAGAI, MASAO
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 027514/0855 →