Semiconductor device with strain
View Patent ↗A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.
1. A semiconductor device comprising:
a semiconductor substrate having an n-channel type transistor region and a p-channel type transistor region;
an element isolation region formed in said semiconductor substrate, said element isolation region defining an n-MOS active region in said n-channel type transistor region and a p-MOS active region in said p-channel type transistor region;
an n-MOS gate electrode structure formed above said semiconductor substrate, traversing an intermediate portion of said n-MOS active region and defining an n-MOS channel region under said n-MOS gate electrode structure;
a p-MOS gate electrode structure formed above said semiconductor substrate, traversing an intermediate portion of said p-MOS active region and defining a p-MOS channel region under said p-MOS gate electrode structure;
a first contact etch stopper film having a tensile stress, formed above said semiconductor substrate and covering said n-channel type transistor region and at least first portions of said element isolation region in said p-channel type transistor region on both sides of the p-MOS active region in gate width direction; and
a second contact etch stopper film having a compressive stress, formed above said semiconductor substrate and covering said p-MOS active region between portions of the first contact etch stopper film covering said at least first portions of said element isolation region; and
wherein said first contact etch stopper film exerts a tensile stress on said n-MOS channel region along a gate length direction, said second contact etch stopper film above said p-MOS active region exerts a compressive stress on said p-MOS channel region along a gate length direction, and said portions of the first contact etch stopper film above said element isolation region in said p-channel type transistor region and said second contact etch stopper film above said p-MOS active region exert a tensile stress on said p-MOS channel region along a gate width direction.
2. The semiconductor device according to claim 1 , wherein said semiconductor substrate is a silicon substrate having a (001) plane and the gate length direction is along <110> direction.
3. The semiconductor device according to claim 1 , wherein the first contact etch stopper film further covers second portions of said element isolation region in said p-channel type transistor region on both sides of the p-MOS active region in gate length direction.