Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.
1. A system for generating a clock signal for an integrated circuit (IC) comprising a plurality of logic paths, comprising:
first and second delay chains configured to produce first and second output signals respectively, wherein a first period of the first output signal is configured to match substantially a first predetermined delay of a first logic path of the plurality of logic paths of the IC, and wherein a second period of the second output signal is configured to match substantially a second predetermined delay of a second logic path of the plurality of logic paths of the IC; and
a clock generator circuit configured to receive the first and second output signals of the first and second delay chains and to produce the clock signal as the slower of the first and second output signals.
2. The system of claim 1 , wherein the first and second delay chains are configured to receive the clock signal as an input.
3. The system of claim 1 , wherein the system is exposed to substantially similar supply voltage and temperature as the IC.
4. The system of claim 1 , wherein the first and second delay chains each includes a ring oscillator circuit.
5. The system of claim 1 , wherein the first and second delay chains each includes a plurality of delay cells in series.
6. The system of claim 5 , wherein at least one of the plurality of delay cells is programmable, thereby allowing the first and second periods of the first and second output signals to be adjusted independently.
7. The system of claim 1 , wherein the first and second periods of the first and second output signals are higher by a predetermined margin than the first and second delays of the first and second logic paths.
8. The system of claim 1 , wherein the first and second logic paths are representative of logic paths in the IC.
9. The system of claim 1 , wherein the first logic path corresponds to a logic path of the IC having a maximum delay among all logic paths of the IC under first operating conditions of the IC, and wherein the second logic path corresponds to a logic path of the IC having the maximum delay among all the logic paths of the IC under second operating conditions of the IC.
10. The system of claim 1 , Wherein the first and second logic paths correspond respectively to a low threshold voltage logic path and a high threshold voltage logic path.
11. The system of claim 1 , wherein rising edges of the clock signal correspond to the latest of rising edges of the first and second output signals, and wherein falling edges of the clock signal correspond to the latest of falling edges of the first and second output signals.
12. The system of claim 1 , further comprising:
a plurality of clock performance monitors (CPMs), each located in a respective part of the IC and each configured to generate an indication of whether or not the clock signal is of adequate frequency for the respective part of the IC; and
a control module configured to control at least one of the first and second delay chains based on the indications generated by the plurality of CPMs.
13. The system of claim 1 , further comprising:
means for turning on/off the system together with the IC, thereby having the system age at substantially the same rate as the IC.
14. A system for generating a clock signal for an integrated circuit (IC), comprising:
a plurality of delay chains, associated with respective logic paths of the IC, configured to produce respective output signals haying respective periods substantially matched to respective predetermined delays of the respective logic paths of the IC; and
a clock generator module configured to produce the clock signal as the slowest of the respective output signals of the plurality of delay chains.
15. The system of claim 14 , wherein at least one of the plurality of delay chains is configured to produce a respective output signal having a respective period substantially matched to a predetermined delay of a low threshold voltage logic path of the IC.
16. The system of claim 14 , wherein at least one of the plurality of delay chains is configured to produce a respective output signal having a respective period substantially matched to a predetermined delay of a high threshold voltage logic path of the IC.
17. The system of claim 14 , further comprising:
means for turning on/off the system together with the IC, thereby having the system age at substantially the same rate as the IC.
18. The system of claim 14 , wherein the system is configured to operate using a same supply voltage as provided to the IC.
19. A method for generating a clock signal for an integrated circuit (IC) comprising a plurality of logic paths, comprising:
generating first and second signals having respective first and second periods that match substantially first and second predetermined delays of respective first and second logic paths of the plurality of logic paths of the IC; and
generating the clock signal as the slower of the first and second signals.
20. The method of claim 19 , wherein the first and second logic paths correspond respectively to a low threshold voltage logic path and a high threshold voltage logic path of the IC.