Methods and apparatus for providing a ML decoding pipeline for QPSK MIMO OFDM receivers
View Patent ↗Methods and apparatus are provided for computing reliability values in a pipeline. A reliability value portion is computed, with control circuitry in a first pipeline stage, based on a difference between a received input signal value and an expected value. The reliability value portion is combined, in a second pipeline stage that follows the first pipeline stage, with a first value derived from the received input signal to generate a first reliability value. A determination is made as to whether to update the first reliability value in a third pipeline stage based on a combination of the first reliability value with a second reliability value that corresponds to a second value derived from the received input signal.
1. A method for performing pipeline computation of a reliability value, the method comprising:
computing, with control circuitry in a first pipeline stage, a reliability value portion based on a difference between a received input signal value and an expected value;
combining, in a second pipeline stage that follows the first pipeline stage, the reliability value portion with a first value derived from the received input signal to generate a first reliability value; and
determining whether to update the first reliability value in a third pipeline stage based on a combination of the first reliability value with a second reliability value that corresponds to a second value derived from the received input signal.
2. The method of claim 1 , wherein the determining comprises computing a plurality of minimum state update values by comparing the first reliability value with the second reliability value, where the second value that is derived from the input signal corresponds to a second bit permutation of a stream of the input signal.
3. The method of claim 1 , wherein the reliability value portion is computed based on all of the bit permutations of some streams of the input signal.
4. The method of claim 1 , further comprising computing, for each bit position of the input signal, a difference between two state update values that correspond to different values of a particular bit position.
5. The method of claim 1 , wherein the first pipeline stage is performed in N clock cycles and the second pipeline stage is performed during a next N clock cycles.
6. The method of claim 1 , wherein first reliability value is updated at each clock cycle and wherein a plurality of reliability values are computed every four clock cycles.
7. The method of claim 1 , wherein the combining comprises computing a first plurality of metric states based on the reliability value portion and a first bit permutation of the input signal.
8. The method of claim 1 , wherein the reliability value portion corresponds to a first tone of the input signal.
9. The method of claim 1 , wherein:
the first reliability value is computed in accordance with:
| u|=Σ|u i |=Σ|y i −H i *x i |
where u is the first reliability value, y i is the input signal, i is a stream index to a stream of the input signal, H is the channel response, and x is an expected transmitted signal vector.
10. The method of claim 9 , wherein the reliability value portion is computed in accordance with:
y i −H i *z i
where z is a subset of some but not all of the vectors of x.
11. A system for performing pipeline computation of a reliability value, the system comprising:
control circuitry configured to:
compute, in a first pipeline stage, a reliability value portion based on a difference between a received input signal value and an expected value;
combine, in a second pipeline stage that follows the first pipeline stage, the reliability value portion with a first value derived from the received input signal to generate a first reliability value; and
determine whether to update the first reliability value in a third pipeline stage based on a combination of the first reliability value with a second reliability value that corresponds to a second value derived from the received input signal.
12. The system of claim 11 , wherein the control circuitry is further configured to compute a plurality of minimum state update values by comparing the first reliability value with the second reliability value, where the second value that is derived from the input signal corresponds to a second bit permutation of a stream of the input signal.
13. The system of claim 11 , wherein the reliability value portion is computed based on all of the bit permutations of some streams of the input signal.
14. The system of claim 11 , wherein the control circuitry is further configured to compute, for each bit position of the input signal, a difference between two state update values that correspond to different values of a particular bit position.
15. The system of claim 11 , wherein the first pipeline stage is performed in N clock cycles and the second pipeline stage is performed during a next N clock cycles.
16. The system of claim 11 , wherein the first reliability value is updated at each clock cycle and wherein a plurality of reliability values are computed every four clock cycles.
17. The system of claim 11 , wherein the control circuitry is further configured to compute a first plurality of metric states based on the reliability value portion and a first bit permutation of the input signal.
18. The system of claim 11 , wherein the reliability value portion corresponds to a first tone of the input signal.
19. The system of claim 11 , wherein:
the first reliability value is computed in accordance with:
| u|=Σ|u i |=Σ|y i −H i *x i |
where u is the first reliability value, y i is the input signal, i is a stream index to a stream of the input signal, H is the channel response, and x is an expected transmitted signal vector.
20. The system of claim 19 , wherein the reliability value portion is computed in accordance with:
y i −H i *z i
where z is a subset of some but not all of the vectors of x.