Thin film transistor, method of fabricating the same, and organic lighting emitting diode display device including the same
View Patent ↗A thin film transistor, a method of fabricating the same, and an organic light emitting diode display device including the same. The thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, including a channel region, source/drain regions, and a body contact region; a gate insulating layer disposed on the semiconductor layer so as to expose the body contact region; a gate electrode disposed on the gate insulating layer, so as to contact the body contact region; an interlayer insulating layer disposed on the gate electrode; and source/drain electrodes disposed on the interlayer insulating layer and electrically connected to the source/drain regions. The body contact region is formed in an edge of the semiconductor layer.
1. A method of fabricating a thin film transistor, the method comprising:
forming a semiconductor layer on a substrate;
forming a gate insulating layer on the semiconductor layer, so as to expose an edge of the semiconductor layer;
forming a gate electrode on the gate insulating layer, which contacts the exposed edge of the semiconductor layer;
forming an interlayer insulating layer on the gate electrode; and
forming source and drain electrodes on the interlayer insulating layer, which are respectively electrically connected to source and drain regions of the semiconductor layer.
2. The method of claim 1 , wherein the exposed edge of the semiconductor layer is connected to the channel region.
3. The method of claim 2 , wherein the width of the exposed edge of the semiconductor layer is not more than about 0.1 μm.
4. The method of claim 2 , further comprising injecting a first type of impurity into the exposed edge of the semiconductor layer, using the gate insulating layer as a mask.
5. The method of claim 1 , wherein the forming of the semiconductor layer and the gate insulating layer comprises:
forming a polycrystalline silicon layer on the substrate;
depositing an insulating layer on the polycrystalline silicon layer; and
performing a one-time patterning process on the polycrystalline silicon layer and the insulating layer, to form the semiconductor layer and the gate insulating layer.
6. The method of claim 5 , wherein the performing of the one-time patterning process on the polycrystalline silicon layer and the insulating layer comprises making a critical dimension (CD) bias of the insulating layer greater than a CD bias of the polycrystalline silicon layer.
7. The method of claim 1 , further comprising:
forming the semiconductor layer by crystallizing an amorphous silicon layer into a polycrystalline silicon layer, using a crystallization inducing metal;
injecting an N-type impurity into the exposed edge of the semiconductor layer, using the gate insulating layer as a mask; and
annealing the substrate to getter the crystallization inducing metal remaining in the semiconductor layer, into the exposed edge of the semiconductor layer.
8. The method of claim 7 , wherein the annealing is performed for from about 30 seconds to about 10 hours, at a temperature of about 450° C. to about 900° C.