Transmit driver circuit
View Patent ↗A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.
1. A driver circuit comprising:
a differential input including a positive input node and a negative input node;
a differential output including a positive output node and a negative output node;
a bias node;
a first T-coil having a first node coupled to the negative output node, a center tap, and a second node coupled to a source of supply voltage;
a second T-coil having a first node coupled to the positive output node, a center tap, and a second node coupled to the source of supply voltage;
a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, and a control node coupled to the bias node;
a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, and a control node coupled to the bias node;
a third transistor having a current path coupled between the first intermediate node and ground, and a control node coupled to the positive input node; and
a fourth transistor having a current path coupled between the second intermediate node and ground, and a control node coupled to the negative input node.
2. The driver circuit of claim 1 , wherein the first and second transistors comprise N-channel transistors.
3. The driver circuit of claim 1 , wherein the third and fourth transistors comprise N-channel transistors.
4. The driver circuit of claim 1 further comprising a first load resistor interposed between the second node of the first T-coil and the source of supply voltage, and a second load resistor interposed between the second node of the second T-coil and the source of supply voltage.
5. The driver circuit of claim 1 further comprising a pair of capacitors coupled between the first intermediate node and ground, and the second intermediate node and ground.
6. The driver circuit of claim 1 further comprising a pair of capacitors coupled between the center tap of the first T-coil and ground, and the center tap of the second T-coil and ground.
7. The driver circuit of claim 1 further comprising a pair of capacitors coupled between the negative output node and ground, and the positive output node and ground.
8. The driver circuit of claim 1 , wherein the bias node comprises a feedback bias node.
9. The driver circuit of claim 1 , wherein the bias node comprises a feedforward bias node.
10. The driver circuit of claim 1 , wherein the source of supply voltage has a value greater than or equal to one volt.
11. A driver circuit comprising:
a differential input including a positive input node and a negative input node;
a differential output including a positive output node and a negative output node;
a bias node;
a first T-coil having a first node coupled to the negative output node, a center tap, and a second node coupled to a source of supply voltage;
a second T-coil having a first node coupled to the positive output node, a center tap, and a second node coupled to the source of supply voltage;
a cascode stage having a first current path coupled between the center tap of the first T-coil and a first intermediate node, a first control node coupled to the bias node, a second current path coupled between the center tap of the second T-coil and a second intermediate node, and a second control node coupled to the bias node;
a differential stage having a first current path coupled between the first intermediate node and ground, a first control node coupled to the positive input node, a second current path coupled between the second intermediate node and ground, and a second control node coupled to the negative input node.
12. The driver circuit of claim 11 , wherein the cascode stage comprises N-channel transistors.
13. The driver circuit of claim 11 , wherein the differential stage comprises N-channel transistors.
14. The driver circuit of claim 11 further comprising a first load resistor interposed between the second node of the first T-coil and the source of supply voltage, and a second load resistor interposed between the second node of the second T-coil and the source of supply voltage.
15. The driver circuit of claim 11 further comprising a pair of capacitors coupled between the first intermediate node and ground, and the second intermediate node and ground.
16. The driver circuit of claim 11 further comprising a pair of capacitors coupled between the center tap of the first T-coil and ground, and the center tap of the second T-coil and ground.
17. The driver circuit of claim 11 further comprising a pair of capacitors coupled between the negative output node and ground, and the positive output node and ground.
18. The driver circuit of claim 11 , wherein the bias node comprises a feedback bias node.
19. The driver circuit of claim 11 , wherein the bias node comprises a feedforward bias node.
20. The driver circuit of claim 11 , wherein the source of supply voltage has a value greater than or equal to one volt.