S12 TX FIR architecture
A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.
1. A TX FIR architecture, comprising:
a mux coupled to a parallel input data;
a delay block coupled to the mux;
a control bus comprising a coefficient register comprising a plurality of FIR coefficients;
a register comprising bits for selecting delays and FIR coefficients; and
a plurality of driver groups coupled to the control bus, the delay block, and the register.
2. The TX FIR architecture of claim 1 , wherein the driver group comprises a first mux coupled to the control bus and the register configured to select a FIR coefficient for a delay tap from a list of defined delay taps for the driver group and a second mux coupled to the delay block and the register configured to select a delayed signal for the delay tap.
3. The TX FIR architecture of claim 2 , wherein the plurality of driver groups comprises seven driver groups, wherein the list of defined delay taps comprises taps one and two for the first driver group, zero and one for the second driver group, one through four for the third driver group, zero through three for the fourth driver group, one through four for the fifth driver group, one, two, four, and five for the sixth driver group, and one, two, four, and six for the seventh driver group.
4. The TX FIR architecture of claim 2 , wherein each driver group further comprises a latch coupled to the second mux, a plurality of buffers coupled to the latch, a plurality of cascading serializer muxes coupled to each latch, and a driver coupled to each series of cascading serializer muxes and the first mux.
5. The TX FIR architecture of claim 4 , wherein the first mux in one or more driver groups is further coupled to an adder.
6. The TX FIR architecture of claim 4 , wherein the adder is coupled to the first mux and the driver is coupled to the adder.
7. The TX FIR architecture of claim 4 , wherein each series of cascading serializer muxes comprises a first group of muxes coupled to a clock signal and a second group of muxes coupled to the first group of muxes and a half rate clock signal.