Host channel adapter with pattern-type DMA
View Patent ↗An input/output (I/O) device includes a memory buffer and off-loading hardware. The off-loading hardware is configured to accept from a host a scatter/gather list including one or more entries. The entries include at least a pattern-type entry that specifies a period of a periodic pattern of addresses that are to be accessed in a memory of the host. The off-loading hardware is configured to transfer data between the memory buffer of the I/O device and the memory of the host by accessing the addresses in the memory of the host in accordance with the periodic pattern at intervals indicated in the period.
1. An input/output (I/O) device, comprising:
a memory buffer; and
off-loading hardware, which is configured to accept from a host a scatter/gather list comprising one or more entries, including at least a pattern-type entry that specifies a period of a two or more periodic patterns of addresses nested in one another, which are to be accessed in a memory of the host, and to transfer data between the memory buffer of the I/O device and the memory of the host by accessing the addresses in the memory of the host in accordance with the periodic patterns at intervals indicated in the period.
2. The device according to claim 1 , wherein the off-loading hardware is configured to access the addresses by scanning the nested periodic patterns.
3. The device according to claim 1 , wherein, by accessing the addresses in accordance with the periodic patterns, the off-loading hardware is configured to access a partial subset of columns of a matrix that is stored, row after row, in a sequential range of the addresses.
4. The device according to claim 1 , wherein, by accessing the addresses in accordance with the periodic patterns, the off-loading hardware is configured to access a partial sub-range of a multi-dimensional data structure that is stored in a sequential range of the addresses.
5. The device according to claim 1 , wherein, by accessing the addresses in accordance with the periodic patterns, the off-loading hardware is configured to interleave two or more data structures that are stored in separate address ranges in the memory of the host.
6. The device according to claim 1 , wherein the scatter/gather list further comprises one or more single-range entries that specify respective contiguous address ranges that are to be accessed in the memory of the host, and wherein the off-loading hardware is configured to distinguish between the pattern-type entry and the single-range entries.
7. The device according to claim 1 , wherein the intervals specify respective offsets relative to a beginning of the period, at which the addresses are to be accessed.
8. The device according to claim 7 , wherein the pattern-type entry specifies a respective number of the addresses that are to be accessed at each of the offsets.
9. The device according to claim 1 , wherein the pattern-type entry specifies a length of the period.
10. The device according to claim 1 , wherein the pattern-type entry specifies a number of times the period is repeated in the periodic patterns.
11. The device according to claim 1 , wherein a size of the pattern-type entry is independent of a number of times the period is repeated in the periodic patterns.
12. A method, comprising:
in an input/output (I/O) device, accepting from a host a scatter/gather list comprising one or more entries, including at least a pattern-type entry that specifies a period of a two or more periodic patterns of addresses nested in one another, which are to be accessed in a memory of the host; and
transferring data between the I/O device and the memory of the host by accessing the addresses in the memory of the host in accordance with the periodic patterns at intervals indicated in the period.
13. The method according to claim 12 , wherein accessing the addresses comprises scanning the nested periodic patterns.
14. The method according to claim 12 , wherein accessing the addresses in accordance with the periodic patterns comprises accessing a partial subset of columns of a matrix that is stored, row after row, in a sequential range of the addresses.
15. The method according to claim 12 , wherein accessing the addresses in accordance with the periodic patterns comprises accessing a partial sub-range of a multi-dimensional data structure that is stored in a sequential range of the addresses.
16. The method according to claim 12 , wherein accessing the addresses in accordance with the periodic patterns comprises interleaving two or more data structures that are stored in separate address ranges in the memory of the host.
17. The method according to claim 12 , wherein the scatter/gather list further comprises one or more single-range entries that specify respective contiguous address ranges that are to be accessed in the memory of the host, and comprising distinguishing between the pattern-type entry and the single-range entries.
18. The method according to claim 12 , wherein the intervals specify respective offsets relative to a beginning of the period, at which the addresses are to be accessed.
19. The method according to claim 18 , wherein the pattern-type entry specifies a respective number of the addresses that are to be accessed at each of the offsets.
20. The method according to claim 12 , wherein the pattern-type entry specifies a length of the period.
21. The method according to claim 12 , wherein the pattern-type entry specifies a number of times the period is repeated in the periodic patterns.
22. The method according to claim 12 , wherein a size of the pattern-type entry is independent of a number of times the period is repeated in the periodic patterns.