Split Gate Oxides for a Laterally Diffused Metal Oxide Semiconductor (LDMOS)
An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device includes a gate oxide positioned between the source region and the drain region, below the gate region. The semiconductor device uses a split gate oxide architecture to form the gate oxide. The gate oxide includes a first gate oxide having a first thickness and a second gate oxide having a second thickness.
1 . A semiconductor device, comprising:
a source region;
a drain region;
a gate region positioned between the source region and the drain region, the gate region being displaced from the drain region; and
a split gate oxide region in contact with the gate region, the split gate oxide region including a first portion having a first thickness and a second portion having a second thickness, the first thickness being substantially greater than the second thickness.
2 . The semiconductor device of claim 1 , further comprising:
a shallow trench isolation (STI) region positioned between the gate region and the drain region.
3 . The semiconductor device of claim 2 , wherein a first side of the STI region is in substantial contact with the drain region.
4 . The semiconductor device of claim 3 , wherein a second side of the STI region is substantially vertically aligned with the gate region such that no substantial overlap exists between the gate region and the STI region.
5 . The semiconductor device of claim 1 , further comprising:
a first well region and a second well region, the first well region contacting the second well region below the gate region.
6 . The semiconductor device of claim 5 , wherein the first well region extends from the source region to the second well region and the second well region extends from the drain region to the first well region.
7 . The semiconductor device of claim 5 , wherein the first portion is in substantial contact with the second portion to form an oxide junction.
8 . The semiconductor device of claim 7 , wherein the gate region includes a first side and a second side, wherein a substantially horizontal distance from the first side to the oxide junction is approximate equal to a second substantially horizontal distance from the second side to the oxide junction.
9 . The semiconductor device of claim 7 , wherein the gate region includes a first side and a second side, wherein a substantially horizontal distance from the first side to the oxide junction is less than a second substantially horizontal distance from the second side to the oxide junction.
10 . The semiconductor device of claim 1 , wherein the source region comprises:
a first source region; and
a second source region lightly doped relative to the first source region, the second source region contacting the split gate oxide region.
11 . A semiconductor device including a drain region that is displaced from a first side of a gate region to form a laterally diffused metal oxide semiconductor (LDMOS), the LDMOS comprising:
a source region positioned adjacent to a second side of the gate region; and
a split gate oxide region in contact with the gate region, the split gate oxide region including a first portion having a first thickness and a second portion having a second thickness, the first thickness being substantially greater than the second thickness.
12 . The LDMOS of claim 11 , further comprising:
a shallow trench isolation (STI) region positioned between the gate region and the drain region.
13 . The LDMOS of claim 12 , wherein a first side of the STI region is in substantial contact with the drain region.
14 . The LDMOS of claim 13 , wherein a second side of the STI region is substantially vertically aligned with the gate region such that no substantial overlap exists between the gate region and the STI region.
15 . The LDMOS of claim 11 , further comprising:
a first well region and a second well region, the first well region contacting the second well region below the gate region.
16 . The LDMOS of claim 15 , wherein the first well region extends from the source region to the second well region and the second well region extends from the drain region to the first well region.
17 . The LDMOS of claim 15 , wherein the first portion is in substantial contact with the second portion to form an oxide junction.
18 . The LDMOS of claim 17 , wherein the gate region includes a first side and a second side, wherein a substantially horizontal distance from the first side to the oxide junction is approximate equal to a second substantially horizontal distance from the second side to the oxide junction.
19 . The LDMOS of claim 17 , wherein the gate region includes a first side and a second side, wherein a substantially horizontal distance from the first side to the oxide junction is less than a second substantially horizontal distance from the second side to the oxide junction.
20 . A semiconductor device, comprising:
a semiconductor substrate,
a first region formed onto the semiconductor substrate forming a source region
a second region formed onto the semiconductor substrate forming a drain region; a third region formed onto the semiconductor substrate above the source region and the drain region forming a gate region; and
a split gate oxide region formed between the semiconductor substrate and the gate region, the split gate oxide region including a first portion having a first thickness and a second portion having, a second thickness, the first thickness being substantially greater than the second thickness.