IP Library Granted Patent US 8,471,594
Granted Patent B2
US 8,471,594 · App. 13/339,394 · Granted Jun 25, 2013

Apparatus and method for obtaining maximum value and minimum value in plurality of digital input signals

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Quick Facts
Patent No.
US 8,471,594
App. No.
13/339,394
Granted
Jun 25, 2013
Kind
B2
Abstract

The present invention relates to a digital signal processing circuit, and more particularly, to a method and apparatus for generating a maximum value or a minimum value used for designing the digital signal processing circuit. An apparatus for obtaining a maximum value or a minimum value from N digital input signals may include N×W bit processing elements to receive an input of W bits of each of the N digital input signals, W OR operators to receive an input of N operation values output from bit processing elements, and to perform an OR operation, respectively, and W inverters to invert an output value for each of the W OR operators.

Claims (25)

1. An apparatus for obtaining a maximum value or a minimum value from N digital input signals, the apparatus comprising:

N×W bit processing elements to receive an input of W bits of each of the N digital input signals;

W OR operators each to receive an input of N operation values output from the bit processing elements, and to perform an OR operation; and

W inverters to invert an output value for each of the W OR operators.

2. The apparatus of claim 1 , wherein each of the bit processing elements comprises:

a NOR gate to perform a NOR operation on an i th bit value W i of one of the digital input signals, and a value Q i corresponding to an output value of an (i+1) th bit processing element that receives an input of an (i+1) th bit value W i+1 , and to output a value E i as a result of the NOR operation;

an AND gate to perform an AND operation on a value RE i corresponding to an output value of one of the W OR operators that performs an OR operation in response to an input of the value E i output as a result of the NOR operation, and the i th bit value W i of the digital input signal; and

an OR gate to perform an OR operation on the value Q i and an output value of the AND gate, and output a value Q i−1 corresponding to an output value of the OR operation.

3. The apparatus for claim 2 , wherein a value Q i−1 output from a previous bit processing element is input as the value Q i input to the NOR gate of a bit processing element that receives an input of an (i−1) th bit value W i−1 of the digital input signal.

4. The apparatus for claim 2 , wherein, when the bit processing element is a bit processing element corresponding to a most significant bit of the digital input signal, a value equivalent to the i th bit value W i is input as the value Q i input to the NOR gate.

5. A method of obtaining a maximum value or a minimum value from N digital input signals, the method comprising:

receiving an input by each of N×W bit processing elements that receive an input of W bits of each of the N digital input signals;

outputting a value Q i−1 and a value E i operated in each of the bit processing elements;

performing an OR operation on the value E i output from the bit processing elements that are at a same position as each of the N digital input signals; and

inverting a value obtained as a result of the OR operation.

6. The method of claim 5 , wherein the outputting comprises:

outputting the value E i by performing a NOR operation on an i th bit value W i of one of the digital input signals, and a value Q i corresponding to an output value of an (i+1) th bit processing element;

performing an AND operation on a value RE i output from W OR operators that each perform an OR operation in response to an input of the value E i output as a result of the NOR operation, and the i th bit value W i of the digital input signal; and

outputting a value Q i−1 by performing an OR operation on the value Q i and an output value resulting from the AND operation.

7. The method of claim 6 , wherein a value Q i−1 output from a previous bit processing element is input to a NOR operator of a bit processing element that receives an input of an (i−1) th bit value W i−1 of the digital input signal.

8. The method of claim 6 , wherein, when the bit processing element is a bit processing element corresponding to a most significant bit of the digital input signal, a value equivalent to the i th bit value W i is input as the value Q i .

9. A method of obtaining a maximum value or a minimum value from N digital input signals, the method comprising:

receiving an input of an inversion of each bit of N×W bit processing elements that receive an input of W bits of each of the N digital input signals;

to outputting a value Q i−1 and a value E i operated in each of the bit processing elements; and

performing an OR operation on the value E i output from the bit processing elements that are at a same position of each of the N digital input signals.

Assignments (1)
ACKNOWLEDGEMENT OF PATENT EXCLUSIVE LICENSE AGREEMENT Recorded Sep 6, 2013
From: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
To: INTELLECTUAL DISCOVERY CO., LTD.
Reel/Frame 031171/0898 →