Semiconductor circuit and display apparatus employing the same
View Patent ↗Disclosed is a display apparatus including two scanning circuits of the same configuration and layout, arranged on either sides of the display part. As long as one of the scanning circuits is in operation, the other scanning circuit is in a state in which no output signal is output.
1. A semiconductor circuit comprising:
a first scanning circuit; and
a second scanning circuit;
each of the first and second scanning circuits including a plurality of unit registers connected in cascade, wherein,
an output terminal of each of the unit registers of the first scanning circuit and an output terminal of each of the unit registers of the second scanning circuit, corresponding to each other, are coupled to each other, and
each of the unit registers of the first and second scanning circuits includes a thin film transistor (TFT) circuit that, responsive to a control signal supplied to a control terminal thereof, switches an output state of said each of the unit registers of the first and second scanning circuits between a state in which an output signal is output and a state in which no output signal is output,
wherein the unit register of each of the first and second scanning circuits is driven by a three-phase clock;
two neighboring phases of the three-phase clock being respectively supplied to first and second clock terminals of the unit register of each of the first and second scanning circuits,
wherein the output terminal of each of the unit registers of each of the first and second scanning circuits is connected to an associated one of a plurality of gate lines, the output terminal of the unit register arranged at a stage other than a final stage of each of the first and second scanning circuits being connected to an input terminal of the unit register arranged at a next stage;
a pulse being supplied to an input terminal of the unit registers of an initial stage of each of the first and second scanning circuits, the pulse delivered to the unit register of the initial stage being transferred to respective trailing side stage unit registers as the pulse phase is shifted from one unit register to the next, wherein
a first signal that prescribes one scanning direction is supplied to the control terminal of the unit register of the first scanning circuit; and
a second signal that prescribes a scanning direction reverse to the one scanning direction is supplied to the control terminal of the unit register of the second scanning circuit,
the second signal being complementary to the first signal, and wherein
the thin film transistor (TFT) circuit of the unit register includes:
a first transistor having a drain and a gate connected to the second clock terminal of the unit register;
a second transistor having a drain connected to a source of the first transistor, having a gate connected to the input terminal of the unit register and having a source connected to a first power supply;
a third transistor having a drain and a gate connected to the input terminal of the unit register;
a fourth transistor having a drain connected to a source of the third transistor, having a gate connected to a connection node between the source of the first transistor and the drain of the second transistor, and having a source connected to the first power supply;
a fifth transistor having a drain connected to the first clock terminal of the unit register, and having a source connected to the output terminal of the unit register;
a sixth transistor having a drain connected to the output terminal of the unit register, and having a gate connected to a connection node between the source of the first transistor and the drain of the second transistor and a gate of the fourth transistor; and
a seventh transistor having a drain connected to a source of the sixth transistor, having a gate connected to the control terminal of the unit register and having a source connected to the first power supply.
2. The semiconductor circuit according to claim 1 , wherein the thin film transistor (TFT) circuit of the unit register further includes an eighth transistor having a drain connected to the first clock terminal, having a source connected to the drain of the fifth transistor, and having a gate connected to the control terminal of the unit register.