IP Library Granted Patent US 8,816,506
Granted Patent B2
US 8,816,506 · App. 13/340,165 · Granted Aug 26, 2014

Semiconductor device and method of manufacturing the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,816,506
App. No.
13/340,165
Granted
Aug 26, 2014
Kind
B2
Abstract

In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.

Claims (55)

1. A semiconductor device comprising:

a semiconductor substrate having a main surface and a back surface positioned on an opposite side to the main surface;

a first insulating film formed on the main surface of the semiconductor substrate;

a first hole formed in the first insulating film;

a second hole formed in the back surface of the semiconductor substrate;

a bump electrode disposed over the first insulating film and having a protruding portion which is formed at least in the first hole and which reaches the inside of the semiconductor substrate in a cross-sectional view;

a second insulating film formed on a side surface of the second hole; and

a conductive film formed in the second hole and electrically connected to the bump electrode,

wherein, in a planar view, a diameter of the protruding portion is smaller than a diameter of the second hole; and

wherein the conductive film is connected to a side surface and a bottom surface of the protruding portion;

wherein the first hole is entirely filled with the bump electrode; and

wherein the second hole is not entirely filled with the conductive film.

2. The semiconductor device according to claim 1 , wherein a protective insulating film is formed at a boundary portion between the bump electrode and the semiconductor substrate so that the bump electrode and the semiconductor substrate are electrically insulated to each other.

3. The semiconductor device according to claim 1 , wherein, in a planar view, a shape of a perimeter of the second hole is circular and a shape of the bump electrode is polygonal.

4. The semiconductor device according to claim 1 , wherein, in a planar view, a shape of a perimeter of the second hole is polygonal and a shape of the bump electrode is circular.

5. The semiconductor device according to claim 1 , wherein the bump electrode has a shape in which a sidewall has an inclination at a portion exposed above the second insulating film.

6. The semiconductor device according to claim 5 , wherein the bump electrode has an inclination at an angle greater than or equal to 45 degrees to less than 70 degrees at a portion exposed above the second insulating film.

7. The semiconductor device according to claim 5 , wherein the bump electrode has an inclination at an angle greater than or equal to 70 degrees to less than 90 degrees at a portion exposed above the second insulating film.

8. The semiconductor device according to claim 1 ,

wherein a pad is formed between the first insulating film and the bump electrode, and

wherein the second hole does not reach the pad.

9. The semiconductor device according to claim 1 ,

wherein the bump electrode includes a first seed layer and a first metal film,

wherein the first seed layer includes Ti or TiW, and

wherein the first metal film includes Au, Cu, Al or Ni.

10. The semiconductor device according to claim 9 ,

wherein the conductive film includes a second seed layer and a second metal film,

wherein the second seed layer includes Ti and Au, or Cr and Au, and

wherein the second metal film includes Au, Cu, Al or Ni.

11. A semiconductor device comprising:

a semiconductor substrate having a main surface and a back surface positioned on an opposite side to the main surface;

a first insulating film formed on the main surface of the semiconductor substrate;

a first hole formed in the first insulating film;

a second hole formed in the back surface of the semiconductor substrate;

a bump electrode disposed over the first insulating film and having a protruding portion which is formed at least in the first hole and which reaches the inside of the semiconductor substrate in a cross-sectional view;

a second insulating film formed on a side surface of the second hole; and

a conductive film formed in the second hole and electrically connected to the bump electrode,

wherein, in a planar view, a diameter of the protruding portion is smaller than a diameter of the second hole;

wherein the conductive film is connected to a side surface and a bottom surface of the protruding portion;

wherein a pad is formed between the first insulating film and the bump electrode; and

wherein the second hole does not reach the pad.

12. The semiconductor device according to claim 11 , wherein a protective insulating film is formed at a boundary portion between the bump electrode and the semiconductor substrate so that the bump electrode and the semiconductor substrate are electrically insulated to each other.

13. The semiconductor device according to claim 11 , wherein, in a planar view, a shape of a perimeter of the second hole is circular and a shape of the bump electrode is polygonal.

14. The semiconductor device according to claim 11 , wherein, in a planar view, a shape of a perimeter of the second hole is polygonal and a shape of the bump electrode is circular.

15. The semiconductor device according to claim 11 , wherein the bump electrode has a shape in which a sidewall has an inclination at a portion exposed above the second insulating film.

16. The semiconductor device according to claim 15 , wherein the bump electrode has an inclination at an angle greater than or equal to 45 degrees to less than 70 degrees at a portion exposed above the second insulating film.

17. The semiconductor device according to claim 15 , wherein the bump electrode has an inclination at an angle greater than or equal to 70 degrees to less than 90 degrees at a portion exposed above the second insulating film.

18. The semiconductor device according to claim 11 ,

wherein the bump electrode includes a first seed layer and a first metal film,

wherein the first seed layer includes Ti or TiW, and

wherein the first metal film includes Au, Cu, Al or Ni.

19. The semiconductor device according to claim 18 ,

wherein the conductive film includes a second seed layer and a second metal film,

wherein the second seed layer includes Ti and Au, or Cr and Au, and

wherein the second metal film includes Au, Cu, Al or Ni.

Assignments (5)
CHANGE OF NAME Recorded Nov 19, 2025
From: TESSERA ADVANCED TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.
Reel/Frame 073635/0304 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2014
From: RENESAS ELECTRONICS CORPORATION
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 032620/0471 →