Apparatus and method for a synchronous multi-port memory

1. A multi-port memory, comprising:

a plurality of ports, each port including

port input logic that generates a write enable value and a read enable value from received control signals, and

a delay stage coupled to store the write enable value from the port input logic, and configured to force the stored write enable value to a disable state in response to an asserted busy signal of the port; and

an arbitration circuit coupled to the ports that arbitrates contending accesses to the ports by de-asserting a busy signal to one port, and asserting a busy signal for all other ports;

control logic that logically combines the read and write enable values of the port to generate an applied write enable value for the port; and

a memory array having write enable inputs coupled to receive the applied write enable values of each port.

2. The multi-port memory of claim 1 , wherein:

each delay stage is further coupled to store address values from the port input logic of the same port.

3. The multi-port memory of claim 2 , wherein:

each port further includes an address multiplexer (MUX) configured to output an address value from the port input logic or an address value stored in the delay stage to a memory array in response to a control input.

4. The multi-port memory of claim 3 , wherein:

each port further includes

the control input of the address MUX being generated in response to the read enable value.

5. The multi-port memory of claim 1 , wherein:

each port further includes a write data delay stage coupled to store write data received at a write data input stage.

6. The multi-port memory of claim 1 , wherein:

each port further includes read path logic configured to selectively output write data stored in either a memory array or the write data delay stage of the port in a read access operation to the port.

7. The multi-port memory of claim 6 , wherein:

each read path logic is further configured to selectively output write data stored in the write data input stage or write data delay stage of another port in a read access operation to the port.

8. A multi-port memory, comprising:

a plurality of ports, each port including

a delay stage that delays address values and write enable values received from an input stage, and

an address multiplexer (MUX) having a first input coupled to receive an address value input to the delay stage, a second input coupled to receive a delayed address value output from the delay stage, a control input coupled to receive a read enable value, and an output coupled to output address values to a memory array, and a read enable latch having an input coupled to receive the read enable value from an input stage and an output coupled to the control input of the address MUX; wherein

each input stage further includes control logic that logically combines read enable signals with write enable signals to generate an applied write enable signal for input to the memory array.

9. The multi-port memory of claim 8 , wherein:

each input stage provides an address value and write enable value to the delay stage in response to a port clock of the port; and

each delay stage outputs a delayed address value and delayed write enable value in response to its port clock.

10. The multi-port memory of claim 9 , wherein:

each port further includes

a write data input stage that provides write data to a write data delay stage in response to its port clock; and

the write data delay stage outputs delayed write data to the memory array in response to its port clock.

11. The multi-port memory of claim 8 , wherein:

each input stage provides address values and write enable values to the delay stage in response to a port clock particular to the port;

each delay stage outputs a delayed address value and delayed write enable value in response to its port clock; and

each read enable latch latches read enable values in response to its port clock.

12. The multi-port memory of claim 8 , further including:

an arbitration circuit coupled to the ports that arbitrates concurrent accesses to the ports by de-asserting a busy signal to one port, and asserting a busy signal for all other ports; and

each delay stage is configured to change its delayed write enable signal in response to the busy signal of its port being asserted.

13. A method, comprising:

storing address, read enable data, and write enable data for competing accesses on different ports of a memory device;

arbitrating between the competing accesses to determine one prevailing access, with the remaining accesses being nonprevailing accesses;

for all nonprevailing accesses that are write accesses, setting the stored write enable data to an inactive value;

logically combining at least the read and write enable data of the same port to generate an applied write enable value; and

controlling write operations to a memory array according to the applied write enable values of the different ports.

14. The method of claim 13 , wherein:

for both prevailing and non-prevailing write accesses, applying the stored address of the port to the memory array.

15. The method of claim 13 , wherein:

storing address and write enable data includes, for each port, clocking the address and write enable data into a delay stage from an input stage according to a port clock for the port.

16. The method of claim 15 , further including:

for each port,

clocking write data from a write data input data stage to a write data delay stage according to the port clock for the port, and

clocking write data from the write data delay stage to a memory array according to the port clock for the port.

17. The method of claim 13 , further including:

for a prevailing read access, applying address data and read enable data from an input stage of the prevailing port to a memory array.

18. The method of claim 17 , wherein:

for nonprevailing read accesses, applying address data and read enable data from the input stages of the ports to the memory array.