Linearization of broadband power amplifiers

1. An RF linearizer for a power amplifier, comprising:

a quadrature up-converter for up-converting a baseband input signal that is to be transmitted by the power amplifier;

an RF analog predistorter controlled by a set of coefficients for predistorting the up-converted input signal;

a down-converter for down-converting an output signal of the power amplifier;

an error monitor receiving the down-converted output signal and the input signal for providing an error signal; and

a signal analyzer receiving the error signal, the signal analyzer using an out-of-band power spectrum of the error signal to optimize the set of coefficients.

2. The RF linearizer of claim 1 , wherein the up-converter up-converts the input signal to an intermediate frequency between baseband and a frequency at which the input signal is to be transmitted.

3. The RF linearizer of claim 2 , wherein the down-converter down-converts the output signal to the intermediate frequency.

4. The RF linearizer of claim 1 , wherein the error monitor comprises one or more track and hold circuits.

5. The RF linearizer of claim 1 , wherein the input signal has an in-phase component and a quadrature component.

6. The RF linearizer of claim 1 , wherein the input signal is filtered by a set of finite impulse response filters prior to being received into the error monitor.

7. The RF linearizer of claim 6 , wherein the finite impulse response filters reduces mean square error in the error signal.

8. The RF linearizer of claim 7 , wherein the set of coefficients reduce the residue mean square error in the error signal.

9. The RF linearizer of claim 1 , wherein the out-of-band power spectrum comprises out-of-band emissions at multiple signal regions.

10. A linearizer for a power amplifier receiving a baseband input signal, comprising:

a baseband analog predistorter for predistorting the baseband input signal comprising one or more polynomial circuits, the polynomial circuits each comprising analog multipliers, summers and one or more complex multipliers and each implementing a polynomial function in the form of

f

⁡

(

x

)

=

∑

k

=

1

n

⁢

a

k

⁢

x

k

,

where n is an integer greater than one; and

an up-converter for up-converting the predistorted baseband input signal to a frequency designated for transmission by the power amplifier.

11. The linearizer of claim 10 , wherein the baseband input signal includes an in-phase component and a quadrature component.

12. The linearizer of claim 10 , wherein the baseband input signal is a digital signal, wherein the linearizer further comprises one or more digital-to-analog converters to provide the baseband input signal as an analog signal to the baseband analog predistorter.

13. The linearizer of claim 10 , further comprises a plurality of summers each provided for eliminating a DC offset voltage associated with each analog multiplier.

14. The linearizer of claim 10 , wherein the baseband analog predistorter further comprises a delay filter for delaying the baseband input signal.

15. The linearizer of claim 14 , wherein the delay filter comprises an off-chip analog delay element.

16. The linearizer of claim 14 , wherein the delay filter comprises a digital delay element.

17. A method for linearizing a power amplifier, comprising:

up-converting a baseband input signal that is to be transmitted by the power amplifier;

predistorting the up-converted input signal in an RF analog predistorter controlled by a set of coefficients;

down-converting an output signal of the power amplifier;

obtaining an error signal that is a difference between the down-converted output signal and the input signal; and

monitoring the error signal in a signal analyzer, the signal analyzer using an out-of-band power spectrum of the error signal to optimize the set of coefficients.

18. The method of claim 17 , wherein the input signal is up-converted to an intermediate frequency between baseband and a frequency at which the input signal is to be transmitted.

19. The method of claim 18 , wherein the output signal is down-converted to the intermediate frequency.

20. The method of claim 17 , wherein the error signal is obtained using one or more track and hold circuits.

21. The method of claim 17 , wherein the baseband input signal has an in-phase component and a quadrature component.

22. The method of claim 17 , further comprising filtering the baseband input signal in a set of finite impulse response filters and providing the filtered signal to obtain the error signal.

23. The method of claim 22 , wherein the finite impulse response filters reduce mean square error in the error signal.

24. The method of claim 23 , wherein the set of coefficients reduce the residue mean square error in the error signal.

25. The method of claim 17 , wherein the out-of-band power spectrum comprises out-of-band emissions at multiple signal regions.

26. A method for linearizing a power amplifier, comprising:

receiving a baseband input signal;

predistorting the baseband input signal in a baseband analog predistorter that comprises one or more polynomial circuits, the polynomial circuits each comprising analog multipliers, summers and one or more complex multipliers and each implementing a polynomial function in the form of

f

⁡

(

x

)

=

∑

k

=

1

n

⁢

a

k

⁢

x

k

,

where n is an integer greater than one; and

up-converting the predistorted baseband input signal to a frequency designated for transmission by the power amplifier.

27. The method of claim 26 , wherein the baseband input signal includes an in-phase component and a quadrature component.

28. The method of claim 26 , wherein the baseband input signal is a digital signal, wherein the method further comprises providing one or more digital-to-analog converters to convert the baseband input signal to an analog signal for the baseband analog predistorter.

29. The method of claim 26 , further comprises providing a summer to eliminate a DC offset voltage associated with each analog multiplier.

30. The method of claim 26 , wherein the baseband analog predistorter further comprises delaying the baseband input signal in a delay filter.

31. The method of claim 30 , wherein the delay filter comprises an off-chip analog delay element.

32. The method of claim 30 , wherein the delay filter comprises a digital delay element.