Wiring substrate and manufacturing method thereof
A wiring substrate includes plural insulating layers including an outermost insulating layer; and plural wiring layers which are alternately laminated between the insulating layers and include outermost wiring layers exposed from the outermost insulating layer and through wirings having electrode pads on end portions of the through wirings and penetrating through the outermost insulating layer, wherein the electrode pads of the through wirings are exposed from the outermost insulating layer, and a part of the outermost wiring layers overlaps the end portions of the through wirings and is connected to the through wirings.
1. A wiring substrate comprising:
a plurality of insulating layers including an outermost insulating layer; and
a plurality of wiring layers which are alternately laminated between the insulating layers and include
outermost wiring layers exposed from the outermost insulating layer, and
through wirings having electrode pads on end portions of the through wirings and penetrating through the outermost insulating layer,
wherein the electrode pads of the through wirings are exposed from the outermost insulating layer, and
a part of the outermost wiring layers overlaps the end portions of the through wirings and is connected to the through wirings,
wherein exposed faces of the through wirings and faces opposite to the exposed faces of the through wirings are circular, and
diameters of the exposed faces are smaller than diameters of the opposite faces of the through wirings,
wherein at least one through wiring of the through wirings contacts an upper surface and side surfaces of an end part of the outermost wiring layers,
wherein the outermost insulating layer contacts an upper surface and side surfaces of parts of the outermost wiring layers other than the end part so that the parts of the outermost wiring layers are embedded in the outermost insulating layer.
2. The wiring substrate according to claim 1 ,
wherein exposed faces of the outermost wiring layers, exposed faces of the end portions of the through wirings and a surface of the outermost insulating layer are arranged on the same plane.
3. The wiring substrate according to claim 1 ,
wherein exposed faces of the outermost wiring layers and the exposed faces of the through wirings are recessed from an outermost lower surface of the outermost insulating layer.
4. The wiring substrate according to claim 1 ,
wherein another part of the outermost wiring layers is wired between the adjacent through wirings.
5. The wiring substrate according to claim 1 ,
wherein other electrode pads are exposed from another outermost insulating layer,
the electrode pads are configured to electrically connect a semiconductor chip, and
the other electrode pads are configured to electrically connect another wiring substrate.